Michael R. Seacrist

Silicon Crystal Growth and Wafer Technologies

Silicon substrates form the foundation of modern microelectronics. Whereas the first 50 years of silicon wafer technology were primarily driven by the microelectronics industry, applications in photovoltaics (PV) also promise to drive new advances in silicon wafer technology over the next ten years. In the first part, we review the historical development of semiconductor silicon wafer technology and highlight recent technical advances in bulk crystal growth and wafering technologies, including the development of silicon-on-insulator (SOI) technologies and ultrathin wafers. We then discuss technologies that could take us beyond the current capabilities of complementary metal-oxide-semiconductor (CMOS) devices. In the second part, we review silicon manufacturing for PV applications and some unique wafering technology challenges in that field. Finally, we summarize industry roadmaps and product needs highlighting key technical areas which promise to shape the future of silicon wafer technologies in the coming decades.

WS2\/Silicon Heterojunction Solar Cells: A CVD Process for the Fabrication of WS2 Films on p-Si Substrates for Photovoltaic and Spectral Responses

With the layer-dependent tunability of their optical band gap in the near-infrared (IR ) to visible spectrum, transition metal dichalcogenides (TMDs), including molybdenum disulfide (MoS2) and tungsten disulfide (WS2), exhibit strong light-matter interactions, making them suitable as absorber layers for optoelectronic devices. Currently, the WS2-based solar cells are fabricated via micromechanical/chemical exfoliation or transfer of two-dimensional (2-D) WS2 layers onto conventional three-dimensional (3-D) bulk semiconductors, which poses a challenge for large-scale integrations and consequent device performances.

Chemical Interaction-Guided, Metal-Free Growth of Large-Area Hexagonal Boron Nitride on Silicon-Based Substrates

Hexagonal boron nitride (h-BN) is an ideal platform for interfacing with two-dimensional (2D) nanomaterials to reduce carrier scattering for high-quality 2D electronics. However, scalable, transfer-free growth of hexagonal boron nitride (h-BN) remains a challenge. Currently, h-BN-based 2D heterostructures require exfoliation or chemical transfer of h-BN grown on metals resulting in small areas or significant interfacial impurities. Here, we demonstrate a surface-chemistry-influenced transfer-free growth of large-area, uniform, and smooth h-BN directly on silicon (Si)-based substrates, including Si, silicon nitride (Si3N4), and silicon dioxide (SiO2), via low-pressure chemical vapor deposition. The growth rates increase with substrate electronegativity, Si < Si3N4 < SiO2, consistent with the adsorption rates calculated for the precursor molecules via atomistic molecular dynamics simulations. Under graphene with high grain density, this h-BN film acts as a polymer-free, planar-dielectric interface increasing carrier mobility by 3.5-fold attributed to reduced surface roughness and charged impurities. This single-step, chemical interaction guided, metal-free growth mechanism of h-BN for graphene heterostructures establishes a potential pathway for the design of complex and integrated 2D-heterostructured circuitry.

Intergrain Diffusion of Carbon Radical for Wafer-Scale, Direct Growth of Graphene on Silicon-Based Dielectrics

Graphene intrinsically hosts charge-carriers with ultrahigh mobility and possesses a high quantum capacitance, which are attractive attributes for nanoelectronic applications requiring graphene-on-substrate base architecture. Most of the current techniques for graphene production rely on the growth on metal catalyst surfaces, followed by a contamination-prone transfer process to put graphene on a desired dielectric substrate. Therefore, a direct graphene deposition process on dielectric surfaces is crucial to avoid polymer-adsorption-related contamination from the transfer process. Here, we present a chemical-diffusion mechanism of a process for transfer-free growth of graphene on silicon-based gate-dielectric substrates via low-pressure chemical vapor deposition. The process relies on the diffusion of catalytically produced carbon radicals through polycrystalline copper (Cu) grain boundaries and their crystallization at the interface of Cu and underneath silicon-based gate-dielectric substrates. The graphene produced exhibits low-defect multilayer domains ( La ∼ 140 nm) with turbostratic orientations as revealed by selected area electron diffraction. Further, graphene growth between Cu and the substrate was 2-fold faster on SiO2/Si(111) substrate than on SiO2/Si(100). The process parameters such as growth temperature and gas compositions (hydrogen (H2)/methane (CH4) flow rate ratio) play critical roles in the formation of high-quality graphene films. The low-temperature back-gating charge transport measurements of the interfacial graphene show density-independent mobility for holes and electrons. Consequently, the analysis of electronic transport at various temperatures reveals a dominant Coulombic scattering, a thermal activation energy (2.0 ± 0.2 meV), and two-dimensional hopping conduction in the graphene field-effect transistor. A band overlapping energy of 2.3 ± 0.4 meV is estimated by employing the simple two-band model.