Michael Raymond Weatherspoon

Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs

Successful implementation of 3D integration technology requires understanding of the unique yield and reliability issues associated with through-silicon vias (TSVs), with adequate design and process considerations to address these issues. This paper relates to the characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs designed for use in 3D Si interposers and 3D wafer-level packaging applications. The paper will describe a variety of methods for characterization of Cu TSV fill quality, microstructure, and thermally-induced TSV height increase known as “copper protrusion” or “copper pumping.” An X-ray imaging method was used for fast, nondestructive analysis of Cu TSV plating profiles and detection of trapped voids. In addition, a plasma focused ion beam (plasma-FIB) process was used to generate high quality cross sections of full TSVs, 50μm in diameter and 150μm depth. Imaging of TSVs by Ga FIB channeling contrast and electron backscattered diffraction (EBSD) provided information about Cu microstructure, including quantitative analysis of grain size. It was observed that TSVs exposed to elevated temperatures exhibited a substantial increase in grain size, which was associated with the Cu protrusion effect. This paper will also report the results of TSV integration with subsequent layers, with analysis of thermo-mechanical failures due to interactions between Cu TSVs and adjacent dielectric layers. The use of an anneal step to stabilize the plated Cu TSVs, prior to build-up of subsequent dielectric layers, will be described.

Thermally enhanced 3 dimensional integrated circuit (TE3DIC) packaging

Commercial packaging roadmaps clearly depict the imminence of chip stacking utilizing through silicon via (TSV) technology (commonly referred to as 3-dimensional integrated circuits (3DIC)) as a means to improve system performance by reducing routing lengths, latency, and drive power while increasing functionality per unit volume. Roadmaps and packaging research focus areas also depict complex 3DIC and packaging architecture concepts to include heterogeneous materials, components and features [1-2]. This added diversity often exacerbates physical proximity effects such as thermal and electromagnetic (EM) coupling. To reduce unwanted thermal and EM coupling, we propose interleaving 25μm thick, flexible, high thermal conductivity (1600 W/m·K, in-plane) pyrolytic graphite sheets (PGS) [3] into 3DIC stacks. The PGS provides passive parallel thermal paths from each die to the package heat spreader with potential significant reduction in overall package thermal resistance (0JC). This also provides design flexibility to thermally decouple sensitive components within the package from intermittent power sources by thermal routing. Interleaving PGS is also expected to impart EM shielding benefits between die and serve to reduce overall package emissions. This paper focuses on potential junction-to-case thermal resistance improvements of a Thermally Enhanced 3-Dimensional Integrated Circuit (TE3DIC) packaging solution. By utilizing a path-finding set of thermal models of a TE3DIC BGA package, design parameters are adjusted to assess various cases, promote design intuition, and ultimately lead to a final test vehicle design. This test vehicle includes three TSV die with both uniform and localized (fireball) Ni80Cr20 heater traces and include resistive platinum temperature sensors. These die are copper pillar bonded with PGS interleaved and flip chip soldered to a 37mm BGA carrier. The perimeter of the PGS is bonded to a terraced copper heat spreader. Detailed modeling estimates a 44% reduction in package thermal resistance with PGS interleaves in a three die stack compared with a similar direct bonded die stack. Reductions are greater for 3DIC designs with copper pillar bonding compared to covalently bonded die stacks.

Engineered polymers for optical interconnects

Specialty optical polymers offer unique solutions based on materials properties that can be engineered to meet specific applications. The development of polymer materials to meet specific requirements for optical interconnects and devices will be described.