Michael T. Frederick

Light trails: a sub-wavelength solution for optical networking

All-optical networks are able to transport data from source to destination entirely in the optical domain. This is a departure from current optical networks that rely on optical-electrical-optical (OEO) conversion at each intermediate connection node to route data properly. The opacity inherent in traditional networks is costly in terms of limiting bandwidth and increasing switching complexity. MPLS, OBS and OPS have been proposed as solutions for realizing an all-optical network. MPLS and OBS have the advantages of creating all-optical connections between nodes, but do not allow intermediate nodes to use the wavelength as well. Additionally, optical switches are constantly being reconfigured to accommodate new connections. OPS can make switching decisions in the optical domain, but the technology is immature. Light trail technology tries to avoid the pitfalls of immature technology, the inability of intermediate nodes to use a connection wavelength, and the constant reconfiguration of switches. A light trail is a unidirectional optical bus between nodes that allows intermediate nodes to access the bus. The goal is to minimize the amount of active switching that needs to be done by allowing intermediate nodes to use a connection that has already been setup. Connections are not constantly being setup and torn down, but rather exist for as long as they are being used by any of the nodes along their light trail.

Sub-graph routing: a generalized fault-tolerant strategy for link failures in WDM optical networks

Single- and multiple-link failure resilience are of critical importance in survivable wavelength division multiplexed (WDM) optical network design. Networks are not made up simply of logical links, but also of links that are physically routed together or share a common node. Links that share a common physical duct are known in literature as shared risk link groups (SRLGs), and their impact on network design is widely studied. This paper presents a complete survivability approach for WDM optical network design known as sub-graph fault tolerance. Sub-graphs are created by removing any combination of components in the network to accommodate specific fault scenarios. Connections in the network are accepted if they can be routed in all predetermined sub-graphs. In this manner, protection against 100% of all multiple- and single-link failure scenarios designated by the designer is achieved, and heuristic best-effort protection is provided against subsequent or simultaneous link failures for which the network is not specifically designed. for which the network has not explicitly provisioned for, is also performed.

Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs

Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource This work presents ChainMap, a polynomial-time delay-optimal technology mapping algorithm for the creation of generic logic chains in LUT-based FPGAs. ChainMap requires no HDL macros be preserved through the design flow. It creates logic chains, both arithmetic and non-arithmetic, in an arbitrary Boolean network whenever depth increasing nodes are encountered. Use of the chain is not reserved for arithmetic, but rather any set of gates exhibiting similar characteristics. By using the carry chain as a generic, near zero-delay adjacent cell interconnection structure an average optimal speedup of 1.4x is revealed, and an average relaxed speedup of 1.25x can be realized simultaneously with a 0.95x LUT utilization decrease

Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics

Ripple-carry architectures are the norm in todays reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric. However, their computation delay grows linearly with operand width. Many different fabric carry-chains have been presented in literature offering non-linear delays, but generally require a significant investment in routing and processing area. Carry-skip chains are well-known in arithmetic logic design, and although they too possess a linear delay, their performance is 2times or more faster than simple ripple-carry schemes. They require an expanded carry chain and minimal extra logic, but offer impressive speed-ups for arithmetic. This paper presents a reconfigurable cell that supports carry-skip arithmetic using a multi-bit carry chain achieving 2 middot k middot b+ n/b performance, where b is the block size and k is an architecture constant. The cell is specialized for arithmetic and Boolean operations with reduced configuration memory. Additional resources are provided to reuse the multi-bit carry chain for 3-source operand arithmetic to explore how multi-bit chains can be reused

Sub-graph routing : a novel fault-tolerant architecture for shared-risk link group failures in WDM optical networks

Failure resilience is one the desired features of the Internet. Multiple link failure models, in the form of shared-risk link group (SRLG) failures, are becoming critical in survivable optical network design. Most of the traditional restoration schemes are based on the single-failure assumption which is unrealistic. In our research, we propose a novel survivability approach that can tolerate multiple failures arising out of SRLG situations. Each network has a set of sub-graphs that can be created by removing each of the links in the network and, in addition, removing all of the links of a SRLG. Connections in the newly proposed strategy are accepted if they can be routed in all the sub-graphs, and are protected against all single link and SRLG failures. We also study how restorability can be achieved for node failures and analyze the performance of our approaches for different network topologies. Our proposed restoration architecture requires the storage of network state information corresponding to each of the possible failure scenarios defined by the subgraphs. This restoration model is novel and can be implemented in current WDM backbone networks.

Hashchip: a shared-resource multi-hash function processor architecture on FPGA

The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. In this paper, we propose and explore multiple architectural options for the HashChip. The HashChip is a hardware architecture aimed at providing a unified solution to the task of message hashing with integrated message padding by aggressive exploitation of similarities in the structure of three commercially popular hash algorithms, namely, MD5, SHA1 and RIPEMD160. A generic approach to prototype digital systems on the Xilinx Virtex 2P embedded FPGA platform is presented and utilized for evaluating the HashChip architectures. The performance of the architectures is studied and evaluated for different design metrics. Throughputs in the range of 200-330 Mbps are obtained on the Xilinx Virtex2P FPGA depending on the input message size and algorithm choice.

Real-time H/W implementation of the approximate discrete Radon transform

The Radon transform (RT) is a widely studied algorithm used to perform image pattern extraction in fields such as computer graphics, medical imagery, and avionics. Real time implementation of the discrete RT (DRT) is extremely difficult due to its use of complex trigonometric functions and O(N/sup 3/) time complexity, making its use in video applications difficult. A O(N/sup 2/lgN) approximate discrete (ADRT) has been presented in literature (Brady, 1998) that allows highly parallel computation. This paper presents an architecture that uses the ADRT to create a computation architecture known as the xADRT. Performance analysis indicates that it can achieve a refresh rate of 10 frames per second for use in real time image processing applications.

Non-arithmetic carry chains for reconfigurable fabrics

Reconfigurable fabrics cater to a wide variety of applications, but have adopted specialized components to allow efficient implementation of performance-critical arithmetic operations. Carry chains have been integrated into the fabric typically as an optimized ripple-carry chain. However, in non-arithmetic operations the carry chain goes unused, when it could be a valuable adjacent-cell interconnect resource. This paper presents a cell architecture facilitating reuse, as well as an analysis of the potential benefits of reuse for an sampling of common of algorithms using commercial FPGAs. Technology map experiments indicate that a variety of applications can benefit from reuse, with utilized routing resources reduced by up to 13% and maximum clock frequency increased by up to 47%.