Michal Kubicek

Z Copy-Controlled Gain-Current Differencing Buffered Amplifier and its applications

The Z Copy-Controlled Gain-Current Differencing Buffered Amplifier (ZC-CG-CDBA) is introduced in the paper. In addition to the well-known CDBA, the input Current Differencing Unit (CDU) is modified and completed by special circuits. Analogously to the conventional CDBA, the z terminal is internally connected to the input of voltage buffer. The current gain from the difference input p, n to the output z can be controlled electronically or by an external device. In addition, an independent high-impedance output zc is available, providing difference current Ip−In. In the paper, the extension of application range of the ZC-CG-CDBA compared with the conventional CDBA is referred to. The novel circuit element is assembled from commercial integrated circuits and its principle is verified experimentally on a universal second-order filter. Copyright

In-system jitter measurement using FPGA

The paper describes architecture, detailed implementation and measurement results of newly developed jitter measurement device. The device is implemented using a single FPGA. Probably the biggest benefit of the proposed method is that it requires no external components, just the FPGA. As such it can be implemented into an existing receiver with an FPGA without any changes to its hardware. The new jitter measurement block was implementer and tested on a real link. Comparison with jitter measurement using an oscilloscope is given to prove its reasonable performance. Compared to previously published jitter measurement methods the module is able to monitor high frequency jitter. It is also very efficient in terms of required hardware resources.

Ethernet bridge for FSO links

The paper deals with a bridge for atmospheric Free-Space Optical links. The atmospheric turbulence causes fades whose duration is typically in the order of tens of milliseconds, which results in the loss of hundreds or thousands of packets. The loss is misinterpreted by the TCP protocol as network congestion and leads to throttling the sender transmission data rate to a fraction of real channel capacity. The proposed Ethernet-to-FSO bridge uses ARQ procedures on the FSO channel to mitigate the packet loss on the link layer. The bridge is based on Xilinx Virtex-5 FPGA with additional memory for buffers. A special link protocol for the FSO path has been designed. FSO frames can carry complete Ethernet frames without fragmentation.

Analysis of CDR with simplified selection of sampling domain

The paper deals with a statistical simulation model for a newly proposed feed-forward blind oversampling Clock and Data Recovery circuit with low hardware complexity. Unlike previous published solutions, where the selected sampling phase is constant on a fixed-length window, the new circuit selects the phase upon the occurrence of several consecutive edges in one sampling domain, i.e. the window length changes randomly. The proposed simulation model is based on periodic Markov chain representation of the domain-selection process. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. Computational complexity is determined by the jitter period length. The model includes random jitter, sinusoidal jitter, and frequency offset of transmit and receive clocks.

Optimization of oversampling Data Recovery

The paper deals with the design and optimization of blind oversampling Clock and Data Recovery (CDR) based on FPGA prototyping. The main advantage of the oversampling CDR is the fully digital architecture, which enables the FPGA-based testing and its subsequent integration into any ASIC technology. The oversampling CDR is a promising block for Free Space Optical (FSO) applications because of its extremely short reacquisition time, which is the key feature for efficient communication over the frequently fading channel. An efficient statistical simulation model for the CDR optimization is presented. Our effort in optimization was focused mainly on the simplification of the decision algorithm while maintaining acceptable jitter tolerance. The suggested method was verified on the Xilinx FPGA platform.

Asynchronous logical system simulation in VHDL

The following article describes the fundamentals of asynchronous logical systems from handshaking protocols to Muller pipeline. Understanding these fundamentals is important to analysing problems. The aim of this article is to solve problems with the design and simulation of asynchronous circuits. The final results are simulation models of a 4-phase bundled-data pipeline and a 4-phase dual-rail pipeline. The simulation models were generated in the simulation tool Modelsim with real gate delays and with zero wire delays.

Non-stationary statistical simulation of blind-oversampling CDR circuits

Statistical approach is the only practical set of methods for reliable simulation of Clock and Data Recovery circuits which operate at low bit-error rates. The paper deals with a statistical simulation model for blind-oversampling CDR circuits, which estimate the center of the data eye by counting the edges in several subintervals that divide the signal period. In the steady-state, the process is described by the multinomial distribution. The developed model simulates the estimation process in the non-stationary case, which allows including sinusoidal jitter, and frequency offset. Some simulation results are presented.

FPGA-based media converter for FSO links

The paper summarises basic principles of free-space optical (FSO) links and their applications. Further an experimental FSO platform is presented. Its main purpose is to demonstrate FSO benefits for last-mile interconnect solution, especially for end users. The realized FSO link transceiver based on FPGA is described in detail, including its expected performance characteristics. The main benefit of the proposed FSO link is its simplicity, low-cost design and protocol transparency. The transceiver uses a single Ethernet cable for both data transmission and power supply. This greatly simplifies and speeds up the link installation procedure. Finally, a pair of FSO transceivers with an integrated media converter were built and are currently in the process of testing.

Statistical analysis of blind-oversampling CDR circuits

The paper deals with two statistical simulation models for feed-forward blind-oversampling Clock and Data Recovery circuits, which determine the center of the data eye by observing the positions of edges in a data stream. The first model describes the traditional averaged phase picking method based on counting the edges in several domains, which divide the signal period. The second model was developed for a newly proposed CDR circuit, which selects the optimum sampling phase upon the occurrence of several consecutive edges in one sampling domain. Its simulation model is based on the periodic Markov chain representation of the domain-selection process. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. The computational complexity of statistical models is determined by the added jitter properties rather than by the actual level of bit-error rate. The models include random jitter, sinusoidal jitter, and frequency offset of transmit and receive clocks.

Simulation of Digital Clock and Data Recovery of Strongly Disturbed Signals

The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphics SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.