Michal Szulc

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

A new hardware implementation of the triangular neighborhood function (TF) for ultra-low power, self-organizing maps (SOM) is presented. Simulations carried out in the software model of this network show that even for low signal resolutions (3–6 bits) performance of the network is not affected. Resolution of the signal at the output of this block has a dominant influence on the circuit complexity as well as the energy consumption. The proposed mechanism is very fast. For a neighborhood range of 15 a delay in the circuit equals 20 ns that allows for data rates of 20–40 MHz, even for large maps with several hundreds neurons.

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18 μm technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.

The concept of a microcontroller with neural-matrix coprocessor for control systems that exploits reconfigurable FPGAs

The new digital architecture of specialized microcontroller with neural coprocessor for efficient real time control systems of robots is presented. The main idea of the paper is to present the on-chip integrated core of the popular microcontroller, program and data memories and the neural-matrix coprocessor. In order to explain the design, the main processor, neural coprocessor and accompanied networks are described. The reconfigurable FPGA matrix has been used as the prototyping platform. It made possible the fast prototyping process. The paper describes also the future work to implement the presented system as ASIC chip.

The Linux As The Operating System For Computational Node Of Custom Computing Machine Class System

The paper presents the application of the modified real-time Linux kernel as the operating system for the computational node of CCM (custom computing machine) class parallel system designed to aid the simulations of three-dimensional electromagnetic field. The computational node is the application-specific design optimized for the implementation in the FPGA. It is based on Xilnx VirtexIIPro FPGA equipped with two embedded cores of the PowerPC processors. The presented real-time kernel is designed to run on one of the cores. The paper details the procedure needed to create the kernel customized for the specific architecture of the system. The software packages and tools utilized in the kernel development process are also presented

Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm2.

The CCM Based Implementation of the Parallel Variant of BiCG Algorithm Suitable for Massively Parallel Computing

The paper presents the implementation of a method for solving the large sparse non-symmetric linear system on the CCM class parallel machine. The method is an adaptation of the well-known biconjugate gradient algorithm. The equations solved results from the FEM based computations of the 3D electromagnetic field with a motion taken into account

Trajectory realization with collision avoidance algorithm

This paper describes the approach to collision avoidance problem for 3-DOF anthropomorphic robot manipulators. The novelty of the approach is the decomposition of 3D space to two 2D spaces. Resulting is the computationally efficient algorithm, suitable for implementation in the real-time systems. Simulation of the anthropomorphic manipulator operating in three dimensional space with obstacles is also presented.

A low power, low chip area decimation filter for Σ - Δ modulator for flywheel MEMS gyro realized in the CMOS 180 nm technology

The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in the proposed approach all filter sections operate at the sampling frequency of the modulator. The low power dissipation is in this case achieved by substantially simpler structure of particular stages. By selecting the oversampling ratio (OSR) of the modulator sufficiently large, e.g. 200, the decimation filter composed of Finite Impulse Response (FIR) filters with equal coefficients does not distort the passband signal. The low chip area results from eliminating a complex selective filter usually placed at the end of the filtering chain in the decimation filter.

The Concept Of The System For Analysis And Simulation Of Neurons And Their Environment

The paper presents the concept of the system for the analysis of the effect of neurochemical processes on activity and structure of biologically realistic neural networks. Detailed are the neurological-based motivation for the work, the overall structure of the system and selected, implemented modules. The paper presents the current state of the systems implementation and the future work