Michel Auguin

A Joint Duty-Cycle and Transmission Power Management for Energy Harvesting WSN

In this paper, we propose a global power management approach for energy harvesting sensor nodes. Our approach is based on a joint duty-cycle optimization and transmission power control. By simultaneously adapting both parameters, the node can maximize the number of transmitted packets while respecting the limited and time-varying amount of available energy. We obtain a high-packet delivery by using an original predictive transmission power control that can efficiently adapt the transmission power to the wireless channel conditions. To accurately model the wireless channel and the node communication hardware, a waveform-level radio frequency simulator has been developed. Simulation results show 6.5 times improvement in energy efficiency and a packet reception ratio which is 9 times more efficient than a recently published technique. A 15% increase in energy efficiency, with respect to a fixed transmission power configuration, has also been observed. Finally, the global power management strategy has been validated on a real wireless sensor networks platform. Experimental results are very similar to those obtained in simulations, and thus confirm the efficiency of our power management approach.

Image processing on a SIMD/SPMD architecture: OPSILA

OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism; and SPMD (single program, multiple data stream), which is an asynchronous mode. It is shown that OPSILA is efficient for a wide variety of image algorithms including low and high level processing. The efficiency of OPSILA is demonstrated for the low-level algorithms, through the implementation of a set of typical operations: local (convolution), global (histogram), and geometric corrections.<<ETX>>

HW / SW partitioning approach for reconfigurable system design

This paper presents a Genetic Algorithm (GA) based approach for Hardware/Software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to an AC-3 decoder function and its performance is compared with a greedy algorithm.

Power Management in Real Time Embedded Systems through Online and Adaptive Interplay of DPM and DVFS Policies

This paper considers the problem of power/energy minimization for periodic real-time tasks that are scheduled over multiprocessor platforms that have dynamic power management (DPM) and dynamic voltage & frequency scaling (DVFS) capabilities. Early research reports that while both DPM and DVFS policies perform well individually for a specific set of conditions, they often outperform each other under different workload and/or architecture configuration. Thus, no single policy fits perfectly all operating conditions. Instead of designing new policies for specific operating conditions, this paper proposes a generic power management scheme, called the Hybrid Power Management (HyPowMan) scheme. This scheme takes a set of well-known existing (DPM and DVFS) policies, each of which performs well for a given set of conditions, and adapts at runtime to the best-performing policy for any given workload. We performed experiments with state-of the-art DPM and DVFS techniques and results show that HyPowMan scheme adapts well to the changing workload and always achieves overall energy savings comparable to the best-performing policy at any point in time.

A framework for modeling and simulating energy harvesting WSN nodes with efficient power management policies

AbstractWireless sensor networks (WSNs) require an extremely energy-efficient design. As sensor nodes have limited power sources, the problem of autonomy is crucial. Energy harvesting provides a potential solution to this problem. However, as current energy harvesters produce only a small amount of energy and their storage capacity is limited, efficient power management techniques must also be considered. In this article we address the problem of modeling and simulating energy harvesting WSN nodes with efficient power management policies. We propose furthermore a framework that permits to describe and simulate an energy harvesting sensor node by using a high level modeling approach based on power consumption and energy harvesting. The node architectural parameters as well as the on-line power management techniques will also be specified. Two new power management architectures will be introduced, taking into account energy-neutral and negative-energy conditions. Simulations results show that the throughput of a sensor node can be improved up to 50% when compared to a state of the art power management algorithm for solar harvesting WSN. The simulation framework is then used to find an efficient system sizing for a solar energy harvesting WSN node.

A codesign experiment in acoustic echo cancellation: GMDFα

Hardware/Software codesign approaches consist generally in Hw/Sw partitioning and scheduling, constrained code generation, hardware and interface synthesis. This paper presents the codesign of an industrial experiment in acoustic echo cancellation (GMDFa algorithm) and emphasizes the partitioning and communication synthesis steps. This experiment points out interesting problems such as data and programs distribution between system memories and modeling communications in the partitioning process.

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)

Recent embedded systems and SOCs design is confronted with the problem of the socalled productivity gap. In order to cope with this problem, authors emphasize on using UML as a system level language, so higher level of abstraction is achieved. However UML in its current form has not yet achieved the maturity necessary to enable its efficient use within current embedded systems and SOCs CAD environments. Consequently a proper tuning of UML to the specificities of such systems has became mandatory. To meet this requirement, many UML profiles have been proposed by both academia and industry. On the other hand enhancements included in UML2.0 has increased UML opportunities to model embedded systems. UML2.0 is qualified to be a component-based which is more suitable for hardware modeling. In this paper we review and compare the most known UML2.0 profiles for embedded systems and SOCs. For each profile, we try to show its defined stereotypes and the corresponding design flow if it exists. We use some objective criteria to highlight the benefits and the pitfalls of each profile.

Communication synthesis and HW/SW integration for embedded system design

The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardware and software components together and providing communications between them are particularly error prone and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.

Hybrid power management in real time embedded systems: an interplay of DVFS and DPM techniques

Energy-aware scheduling of real time applications over multiprocessor systems is considered in this paper. Early research reports that while various energy-saving policies, for instance Dynamic Power Management (DPM) and Dynamic Voltage & Frequency scaling (DVFS) policies, perform well individually for a specific set of operating conditions, they often outperform each other under different workload and/or architecture configuration. Thus, no single policy fits perfectly all operating conditions. Instead of designing new policies for specific operating conditions, this paper proposes a generic power/energy management scheme that takes a set of well-known existing (DPM and DVFS) policies, each of which performs well for a set of conditions, and adapts at runtime to the best-performing policy for any given workload. Experiments are performed using state-of the-art DPM and DVFS policies and the results show that our proposed scheme adapts well to the changing workload and always achieves overall energy savings comparable to that of best-performing policy at any point in time.

An inter-task real time DVFS scheme for multiprocessor embedded systems

In this paper1, we have addressed energy-efficient scheduling of real time applications intended to be executed on multiprocessor systems. Our proposed technique, called Deterministic Stretch-to-Fit (DSF) technique, is based on inter-task real time dynamic voltage and frequency scaling (RT-DVFS). It mainly comprises of three components. Firstly, we propose an online algorithm to reclaim energy by adapting to the variations in actual workload of target application tasks. Secondly, we extend our online algorithm with an adaptive and speculative speed adjustment mechanism. This mechanism anticipates early completion of future task instances based on the information of their average workload. Thirdly, we propose a one-task extension technique for multi-task multiprocessor systems. No real time constraints of target application are violated while applying our proposed technique. Simulation results show that our online slack reclamation algorithm alone gives up to 53% gains on energy consumption and our extended speculative speed adjustment mechanism, along with the one-task extension technique, gives additional gains, reaching a theoretical low-bound on the scalable frequency and voltage.