Michel Campovecchio

New design method of uniform and nonuniform distributed power amplifiers

A new design methodology of uniform and nonuniform distributed power amplifiers is reported in this paper. This method is based on analytical expressions of the optimum input and output artificial lines making up the uniform and nonuniform distributed architectures. These relationships are derived from the load-line requirement of each transistor size for optimum power operation. Furthermore, specific design criteria are presented to enable an efficient choice between uniform and nonuniform distributed architectures. To validate this new design methodology, a nonuniform distributed power amplifier has been manufactured at the TriQuint Semiconductor Foundry, Richardson, TX, using a 0.25-/spl mu/m power pseudomorphic high electron-mobility process. This single-stage monolithic-microwave integrated-circuit amplifier is made of six nonuniform cells and demonstrates 1-W output power with 7-dB associated gain and 20% power-added efficiency over a multioctave bandwidth.

Optimum design of distributed power-FET amplifiers. Application to a 2-18 GHz MMIC module exhibiting improved power performances

A suitable and effective design method of distributed power amplifiers, based on the optimum FET load requirement for power operation, is proposed in this paper. An analytical determination of the gate and drain line characteristic admittances provides both the initial values and right directions for an optimum design. The best trade-offs between wide band and high power operation have been investigated. To validate the method, a FET amplifier demonstrator with a gate periphery of 1.2 mm has been manufactured at the Texas Instruments foundry. The MMIC amplifier demonstrated state of the art power density performance of 340 mW/mm over the 2-18 GHz band associated with 14.2% power added efficiency, 26.5% drain efficiency and 26.1 dBm output power at 1 dB compression in CW operation.<<ETX>>

New design method of non-uniform distributed power amplifiers. Application to a single stage 1 W PHEMT MMIC

A new design methodology of non-uniform distributed power amplifiers is reported in this paper. This method is based on analytical expressions of the optimum input and output artificial lines making up the non-uniform distributed power amplifier. These relationships are based on the optimum load line requirement for power operation. To validate the proposed design methodology, a non-uniform distributed power amplifier has been manufactured at the TriQuint Semiconductor foundry using a 0.25 /spl mu/m power PHEMT process. This single stage MMIC amplifier is made of six non-uniform cells and demonstrates 1 W output power with 7 dB associated gain and 20% PAE over multi-octave bandwidth.

Large signal design method of distributed power amplifiers applied to a 2–18-GHz GaAs chip exhibiting high power density performances

A suitable large signal design method of distributed power amplifiers, based on the optimum FET load requirement for high power operation, is proposed in this article. The gate and drain line characteristic admittances are determined, providing both the initial values and right directions for an optimum design. To validate the proposed design method, a FET amplifier demonstrator with a gate periphery of 1.2 mm has been manufactured at the Texas Instruments foundry. The MMIC distributed amplifier demonstrated an improved power density performance of 340 mW/mm over the 2-18-GHz frequency band associated with a minimum of 13% power-added efficiency and 24% drain efficiency at 1-dB compression in CW operation

Modelling of a 4-18 GHz 6 W flip-chip integrated power amplifier based on GaN HEMTs technology

This paper reports on the design of a cascode GaN HEMT distributed power amplifier demonstrating significant improvement of the best power performances reported to date. The active device is a 8/spl times/50 /spl mu/m AlGaN/GaN HEMT grown on siSiC. The distributed power amplifier integrates 4 cascode cells capacitively coupled to the gate line for power optimization. The active part made of the 4 cascode cells is implanted on a GaN-based wafer while the distributed passive part made of the interconnection lines is implanted on an AlN substrate. Finally, the GaN-based wafer integrating the active part is flip-chipped onto the AlN substrate via electrical and mechanical bumps. The flip-chip integrated circuit demonstrates a mean gain of 10 dB and input/output matching lower than -10 dB over the 4-18 GHz bandwidth. At an input power of 29 dBm (1 db comp.), power simulations exhibit a mean output power of 37.6 dBm with a standard deviation of 0.3 dB, a power gain of 8.6 dB and 16% of PAE over the band. At an input power of 31 dBm (2 dB comp.), the distributed amplifier achieves a mean output power of 38.6 dBm, a power gain of 7.6 dB and 18% of PAE.This paper reports on the design of a cascode GaN HEMT distributed power amplifier demonstrating significant improvement of the best power performances reported to date. The active device is 8 /spl times/ 50 /spl mu/m AlGaN/GaN HEMT grown on siSiC. The distributed power amplifier integrates 4 cascode cells capacitively coupled to the gate line for power optimization. The active part made of the 4 cascode cells is implanted on a GaN-based wafer while the distributed passive part made of the interconnection lines is implanted on an AlN substrate. Finally, the GaN-based wafer integrating the active part is flip-chipped onto the AlN substrate via electrical and mechanical bumps. The flip-chip integrated circuit demonstrates a mean gain of 10dB and input/output matching lower than -10dB over the 4-18GHz bandwidth. At an input power of 29dBm (1 dB comp.), power simulations exhibit a mean output power of 37.6dBm with a standard deviation of 0.3dB, a power gain of 8.6dB and 16% of PAE over the band. At an input power of 31dBm (2dB comp.), the distributed amplifier achieves a mean output power of 38.6dBm, a power gain of 7.6dB and 18% of PAE.

Stability Analysis of Millimeter-Wave Circuits. Application to DC-40GHz PHEMT amplifier and Ku-band HBT power amplifier

Specific CAD oriented methods have been developed [1] for linear and non-linear stability analysis. Both methods are applied to multi-transistor MMIC circuits. These approaches can be easily implemented on any CAD packages and enable linear and non-linear stability to be analysed with a localization of instability paths within an N-transistor circuit. Simulations and measurements of two MMIC circuits (DC-40GHz PHEMT amplifier for optical links and Ku-band HBT power amplifier) demonstrate the efficiency of the proposed methods during the MMIC design processs.

Comparative analysis of CML and MOS differential Automatic Amplitude Level control regulators for built-in-self-test applications

This paper presents Automatic Amplitude Level Regulators (AALR) as a practical Built-In-Test (BIST) and demonstrates its application for on-chip testing and local Calibration of integrated RF blocks. The proposed circuit performs full-wave rectification and generates a dc voltage proportional to the amplitude of an RF signal over a wide frequency range. Both CML and MOS RF AALR are designed and fabricated using NXP-Semiconductors advanced BiCMOS technology process. Very low area occupation with low power consumption are demonstrated for a wide-range of RF input signal power. Digitally controlled bits are introduced for scalable amplitude-level adjustment and control. Measurements show that fabricated RF test devices demonstrate detection dynamic range of 21 dB from 25 MHz to 5 GHz. Advantages and limitations of designed CML and MOS RF regulators are drawn based on careful correlation analysis between simulations and measurement results.

Multiharmonic Volterra Model Dedicated to the Design of Wideband and Highly Efficient GaN Power Amplifiers

This paper presents a complete validation of the new behavioral model called the multiharmonic Volterra (MHV) model for designing wideband and highly efficient power amplifiers with packaged transistors in computer-aided design (CAD) software. The proposed model topology is based on the principle of the harmonic superposition introduced by the Agilent X-parameters, which is combined with the dynamic Volterra theory to give an MHV model that can handle short-term memory effects. The MHV models of 10- and 100-W packaged GaN transistors have been extracted from time-domain load-pull measurements under continuous wave and pulsed modes, respectively. Both MHV models have been implemented into CAD software to design 10- and 85-W power amplifiers in L- and S-bands. Finally, the first power amplifier exhibited mean measured values of 10-W output power and 65% power-added efficiency over 36% bandwidth centered at 2.2 GHz, while the second one exhibited 85-W output power and 65% drain efficiency over 50% bandwidth centered at 1.6 GHz.

Built-in Self Test for Error Vector Magnitude measurement of RF transceiver

In Wireless systems, the overall quality of transmission and reception is determined by various baseband and RF system specifications. The Error Vector Magnitude (EVM) is a measure of the digital modulation quality of the wireless system-under-test which is very sensitive to much impairment in the transceiver. However the EVM test takes a long time and requires expansive Automatic Test Equipment (ATE) in Production. The originality of the proposed approach lies in its ability to overcome two limitations being faced by available techniques (correction signal, reference synchronization, correlation analysis), in addition to length frame reduction. In order to decrease the test cost, time and length sequence, a new EVM measurement method using Built-in Self Test (BIST) is proposed in this paper. Using a digital phase shifter and a multiplier, a reduced QPSK data sequence minimizes the test time and covers the faults such as IQ impairments and amplification distortions. The BIST method demonstrates only 1% difference compared to the usual EVM method and is 1000 times faster than the traditional EVM test (it takes 200µs).

A novel time domain characterization technique of intermodulation in microwave transistors: application to the visualization of the distortion of high efficiency power amplifiers

Along with the increasing necessity of improving the large signal characterization of microwave transistors and the validation of nonlinear models, a novel characterization has emerged based on a time domain approach. As explained and illustrated in this paper, this method allows the visualization and the accurate determination of amplifier distortions at low, medium and large RF power levels. The extraction of single tone and multitone voltage/current waveforms from a dedicated measurement system enhances the novel characterization technique proposed and the validation of non linear electrothermal model for CAD. Examples of measured and simulated results of GaAs FETs and GaInP/GaAs HBTs are given to demonstrate the great possibilities offered by the characterization procedure. Its use to optimize trade-offs between efficiency and linearity of power amplifiers is clearly demonstrated by the display and the visualization of the envelop and carrier distortions of the signals at both ports of power FETs and HBTs.