Michel J. Declercq

Remotely powered addressable UHF RFID integrated system

This paper presents a fully integrated remotely powered and addressable radio frequency identification (RFID) transponder working at 2.45 GHz. The achieved operating range at 4 W effective isotropically radiated power (EIRP) base-station transmit power is 12 m. The integrated circuit (IC) is implemented in a 0.5 /spl mu/m silicon-on-sapphire technology. A state-of-the-art rectifier design achieving 37% of global efficiency is embedded to supply energy to the transponder. The necessary input power to operate the transponder is about 2.7 /spl mu/W. Reader to transponder communication is obtained using on-off keying (OOK) modulation while transponder to reader communication is ensured using the amplitude shift keying (ASK) backscattering modulation technique. Inductive matching between the antenna and the transponder IC is used to further optimize the operating range.

A model for /spl mu/-power rectifier analysis and design

This paper proposes a linear two-port model for an N-stage modified-Greinacher full-wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameter values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. To validate the model a three-stage modified-Greinacher full-wave rectifier was realized in an silicon-on-sapphire (SOS) CMOS 0.5-/spl mu/m technology. The measurements are in excellent agreement with the values calculated using the presented model.

A 2-V 600-/spl mu/A 1-GHz BiCMOS super-regenerative receiver for ISM applications

A 1-GHz receiver, integrated in a 0.8-/spl mu/m BiCMOS technology, consumes 1.2 mW at 2 V. Based on super-regeneration, it is dedicated to short-range data exchange up to 100 kbits/s. Sensitivity of -98 dBm is achieved for a selectivity of 100 kHz. The size of the chip is smaller than 1 mm/sup 2/.

Improvement of power efficiency of inductive links for implantable devices

This paper presents the analysis of inductive links for remote powering of implantable devices and a method to improve the power link efficiency by modifying the geometrical parameters of planar spiral inductors. The analysis of the inductive links includes a model for the inductors, which is more accurate for larger bandwidths. The corresponding equations for the power and voltage transfer functions in the inductive links are solved by using MATLABpsilas Symbolic Math Toolbox. These equations are verified in Agilent ADS, and the results perfectly match. Besides the analysis, a method to improve the power efficiency by changing the geometrical parameters of the spiral inductors is proposed.

Frequency-interleaving technique for high-speed A/D conversion

This paper introduces a concept of analog-to-digital conversion for very high-speed applications. Like the time-interleaving conversion, this method uses different conventional ADCs (channels), which work in parallel, but the approach is different. The basic principle is close to techniques used in signal processing, such as the discrete Fourier transform (DFT) and sub-band coding. Because of its low sensitivity to sampling-clock jitter; this technique can achieve a 6 bit effective accuracy up to the Nyquist frequency.

Inductive Power Link for a Wireless Cortical Implant With Two-Body Packaging

This paper presents an inductive power link for remote powering of a wireless cortical implant. The link includes a Class-E power amplifier, a gate driver, an inductive link, and an integrated rectifier. The coils of the inductive link are designed and optimized for remote powering from a distance of 10 mm (scalp thickness). The power amplifier is designed in order to allow closed-loop control of the power delivered to the implant, by controlling the supply voltage. Moreover, a gate driver is added to the system to drive the power amplifier and to characterize the gate losses. A new packaging topology is proposed in order to position the implant inside a hole in the cranial bone, without occupying a large area, but still obtaining a short distance between the remote powering coils. The package is fabricated by using biocompatible materials such as PDMS and Parylene-C. The power efficiency of the remote powering link is characterized for a wide range of load power (1-20 mW) delivered from the rectifier and is measured to be 24.6% at nominal load of 10 mW.

Capacitorless 1T DRAM sensing scheme with automatic reference generation

To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state 1, the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-/spl mu/m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.

A Closed-Loop Remote Powering Link for Wireless Cortical Implants

This paper presents a closed-loop remote powering link for wireless cortical implants. The link operates from a single power supply at the external reader and delivers power to the implant adaptively under changing load conditions. A feedback information is sent from the implant to the external reader about the power consumption in the implant and the external reader adapts the amount of transmitted power depending on this feedback. In addition, an in vitro measurement setup is fabricated in order to characterize the performance of the wireless energy transfer when the implant is immersed into saline solution. The implant is packaged by using biocompatible materials and the operation of the remote powering link is demonstrated in air and in vitro for a wide range of load power delivered from the voltage regulator. The power transfer efficiency of the overall closed-loop remote powering link is measured to be 10.6% in vitro at nominal load power of 10 mW. Finally, the operation of the implant in vitro is demonstrated over a five-week period.

Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs

The substrate noise coupling problems in todays complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18-

This paper describes a receiver system design for impulse-radio ultra-wideband (IR-UWB) that operates at two carrier frequencies-3.494 and 3.993 GHz-with a 10-Mbps data rate. To reduce the power consumption of the front-end amplifiers, a super-regenerative architecture is used. An integrated circuit, implemented in a CMOS 0.18-μm technology and operating with a 1.5-V power supply, exhibits energy consumption of 0.24 nJ/bit with a measured sensitivity of -66 and -61 dBm at 3.494 and 3.993 GHz, respectively, with a BER of 10-3. Also included on the integrated circuit is an automatic tuning circuit based on a digital phase-locked loop that is used to set the resonant frequency of the super-regenerative block.