Michel Sarlotte

Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM

In the scope of the US Department of Defense (DoD) Joint Tactical Radio System (JTRS) program, the portability and reconfigurability needs of software defined radios (SDR) required by the software communications architecture (SCA) can be resolved thanks to model driven architecture (MDA) and component/container paradigm to address a heterogeneous hardware and software architecture. In this paper, we propose SystemC transaction level modelling (TLM) to simulate platform independent model (PIM) and platform specific model (PSM) of SDRs, while keeping the component/container approach for applications portability. We show that SystemC 2.1 enables natively to simulate the waveform PIM specified in UML to obtain an executable specification, which can be reused to validate the SystemC TLM model of PSM. This latter allows radio platform virtualisation and true reuse of IPs models to validate earlier SDR waveforms and platforms

Mapping semantics of CORBA IDL and GIOP to open core protocol for portability and interoperability of SDR waveform components

Patterns, middlewares and frameworks have been used for decades in software architecture to address the main problems encountered today by the MPSoC and NoC communities: heterogeneity of languages, programming models, simulation/execution environments, interaction semantics and communication protocols. A complete semantics mapping of CORBA interface definition language (IDL) and general inter-ORB protocol (GIOP) on the open core protocol (OCP) has been investigated for hardware components. This mapping is generic, highly configurable and illustrated through our target application: software defined radio.

Embedded Software in Digital AM-FM Chipset

The new standard DRM (digital radio mondial) for digital radio broadcast in the AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently designed based upon an ARM9 multi-core architecture. This paper introduces the application itself, the HW architecture of the SoC, and the SW architecture which includes physical layer, receiver management, the application layer and the global scheduler, based on a real-time OS. Then, the paper presents the HW/SW partitioning and SW breakdown between the various processing cores. The methodology used in the project to develop, to validate and to integrate the SW, covering various methods such as simulation, emulation and co-validation is described. Key points and critical issues are also addressed. One of the challenges is to integrate the whole receiver in the mono-chip with respect to the real-time constraints linked to the audio services.

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.

High data rate fully flexible SDR modem: advanced configurable architecture & development methodology

With the multiplication of mobile and wireless communication networks and standards, the physical layer of communication systems (i.e. the modem part of the system) has to be completely flexible. This assumption leads to the well known Software Defined Radio concept which enables the implementation and the deployment of different waveforms on the same platform. This concept has been widely investigated since the early 2000s mainly for processors and Sw approach but less for reconfigurable Hw or DSP implementation. This paper deals with a specific architecture and an innovative design methodology which were designed within the framework of a fully flexible high data rate Software Defined Radio wireless modem. This approach is focused on the waveform part of the system and its goal is to reach a fully flexible physical layer. In case of modem evolutions or upgrades, it enables to avoid significant rework and extra cost in term of waveform development. Moreover the association of the right architecture and the right methodology allows to master and to manage the complexity of the modem (which presents several hundred configurations available with different kind of parameters) and permits to provide the needed flexibility. The development methodology is based on a C/C++ approach which allows to manage all the parameters at a system level. The architecture coupled to this development methodology offers a high level of modularity which enables to easily modify the waveform only in replacing blocks by other blocks. The efficiency and the flexibility of the modem is then obtained by designing not a single waveform but a waveforms family.

The MOSART Mapping Optimization for Multi-Core ARchiTectures

MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

ENOSYS FP7 EU project: An integrated modeling and synthesis flow for embedded systems design

The ENOSYS project, funded by the EC, aims to shorten the time-to-market of high-performance SoCs by providing design and tool flows for the design and the implementation of embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis, code optimization and design space exploration. The objective here is to automatically generate code, for implementation in execution platforms such as FPGAs, from validated high level designs incorporating initial end user requirements, system functional and non-functional description, platform modelling. This paper describes the design flow developed in the context of the ENOSYS project and the results of a first industrial evaluation through two industrial test cases.

Démarche de conception d’une plate-forme monopuce de réception de radiodiffusion numérique DRM

RésuméLa norme émergentedrm pour la radiodiffusion numérique dans la bandeam nécessite des solutions intégrées à bas coût et faible consommation pour les récepteurs grand public. Un jeu de puces a été développé sur une base bi-processeurarm9. Cet article introduit l’application et la forme d’onde puis présente le processus de développement suivi pour la spécification et la conception de la puce. L’ensemble couvert va du partitionnement matériel/logiciel à la phase de validation en passant par la définition de l’architecture. La partierf est également brièvement présentée compte tenu de son influence sur le circuit en bande de base. Les aspects juridiques sont ensuite abordés. Pour conclure, l’article présente les prochaines étapes liées à ce développement et la rupture méthodologique dans la conception de systèmes sur silicium.AbstractThe newdrm standard for digital radio broadcast in theam band requires integrated devices for radio receivers at low cost and very low power. A chipset has been developed based on anarm9 dual-core architecture. This paper introduces the application itself, and then presents the development process followed to design such a chip covering the hardware/software partitioning, the architecture definition and all the validation issues. Therf part that partially drives the baseband is also briefly presented. The legal aspects are also investigated. Then as a conclusion, this paper presents the next steps of this development and the methodological gap in the system on chip design process.

Embedded SW in Digital AM-FM Chipset

DRM, the new standard for digital radio broadcasting in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently designed based upon an ARM9 multi-core architecture. This paper introduces the application itself, the HW architecture of the SoC and the SW architecture which includes physical layer, receiver management, the application layer and the global scheduler based on a real-time OS. Then, the paper presents the HW/SW partitioning and SW breakdown between the various processing cores. The methodology used in the project to develop, validate and integrate the SW covering various methods such as simulation, emulation and co-validation is described. Key points and critical issues are also addressed.