Michele Borgatti

A geometric approach to maximum-speed n-dimensional continuous linear interpolation in rectangular grids

An algorithm for the linear interpolation of multi-input functions sampled on rectangular grids is presented. A geometric approach is adopted and the mathematics is thoroughly developed. We show that the algorithm is optimum. In fact, when the number n of inputs grows to infinity its computational requirement is O(n log n), which is the same as the lower-bound on the cost of continuous linear interpolation procedures.

Automatic implementation of piecewise-linear fuzzy systems addressing memory-performance trade-off

Many applications of fuzzy controllers are related to complex and fast systems, and require many inputs and rules as well as specific hardware for real-time processing. Hence, many recent investigations and products (e.g. [l]-[5]) aim at coupling speed with complexity.

A low-power integrated circuit for remote speech recognition

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 /spl mu/W at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-/spl mu/m, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 /spl mu/J. It achieves recognition rates over 98% in isolated-word speech recognition tasks.

A low-power, voice-controlled, H.263 video decoder for portable applications

In this paper, a low-power, low-voltage, voice-controlled H.263 video decoding system is presented. Its power consumption makes it suitable for portable systems with limited battery resources. Video decoding of quarter-common intermediate format (QCIF) images at 25 frames per second is achieved at 1-MHz clock frequency and requires about 60 /spl mu/W at 1-V power supply, Sub-QCIF and CIF image formats are also supported. The decoder circuit is controlled by the on-chip isolated word speech recognizer. It is used to implement command-oriented and menu-based applications. The resulting system is expandable taking additional external devices under voice control. The chip integrates 650-k transistors in a 36-mm/sup 2/ area and has been implemented using a standard CMOS 0.35-/spl mu/m, five-metal technology process. The system works correctly down to 0.9 V, allowing single-cell button battery operation.

A smoothly upgradable approach to virtual emulation of HW/SW systems

This article presents a novel approach to the high-level system verification problem based on a hybrid hardware/software virtual emulation tool. Unavailable components or sub-systems are physically replaced on a prototype board by FPGAs whose electrical behavior is driven by software simulations of high-level description models. Such a prototype can smoothly evolve towards the final system as soon as the unavailable parts or the components under manufacturing become available. The simultaneous use of prototyping techniques such as field-programmable circuit boards with software simulation significantly improve the usefulness of our framework. A low-cost verification environment, with multiprocessing and multilanguage capabilities currently in use at University of Bologna, is described.

A 1 V 350 /spl mu/W voice-controlled H.263 video decoder for portable applications

This micro-power voice-controlled video-telephone decoder is suitable for portable button-battery applications. The system is composed of three main logical units selected from a library of reusable low-power macro-cells: a speech recognizer (SR), a programmable system controller (PSC) and a H.263 decoder. The system is expandable through an asynchronous peripheral bus directly connected to the on-chip PSC.

A low-power VLSI feature extractor for speech recognition

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 /spl mu/W at 0.9 V.

A 1 V, 25 /spl mu/W speech recognizer for portable systems

The design and implementation of a speech recognizer in a silicon megacell for single-chip, voice-controlled systems is presented. It has been implemented in a 0.35 /spl mu/m, 5-metal standard-cell CMOS technology. Minimum operating voltage is 0.8 V and average power consumption for one-word recognition is 25 /spl mu/W at the typical clock rate of 1 MHz. Recognition performance is above 95% for both speaker-dependent and multi-speaker small vocabulary tasks. The proposed speech recognition megacell is well suited to be used as building block for portable single-battery driven systems with command-oriented vocal interfaces.

Fast board-level prototyping of a speech recognition system using virtual emulation

This paper presents the board-level prototype implementation of a complete speech recognition system. The recognition system is based on a chip set still under development and, in its final implementation, it will perform real-time isolated-word recognition of up to 1000 word templates. In this paper we show that virtual emulation is an effective approach to high-level system prototyping and verification and achieves a smooth evolution of the prototype to its final implementation. Methodology guidelines are given to handle designs having subsystems whose clock speeds cannot be slowed down at the virtual emulation speed. The case of a real-time speech acquisition user interface is presented. In addition, speed-up techniques providing a threefold improvement in emulation time are discussed. The board-level prototype system has been designed, built and tested in 2 man/months.

A VLSI array processor accelerator for k-NN classification

This paper describes a VLSI array processor system that has been designed and built for classification problems based on the k-nearest neighbors approach. This architecture is suitable for different pattern recognition applications and is scalable to reduce the computation time. A prototype board with two processors has been built and a software driver has been written showing a speed up of 30 times over a software algorithm running on a Sun SPARC20 workstation.