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Dive into the research topics where Michiaki Matsuo is active.

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Featured researches published by Michiaki Matsuo.


IEEE Transactions on Microwave Theory and Techniques | 2001

Dual-mode stepped-impedance ring resonator for bandpass filter applications

Michiaki Matsuo; Hiroyuki Yabuki; Mitsuo Makimoto

It is well known that two orthogonal resonant modes exist within a one-wavelength ring resonator. In this paper, we focus on a ring resonator possessing an impedance step as a form of perturbation. A convenient analyzing method for obtaining the resonance characteristics of this resonator structure is presented. Furthermore, generation of attenuation poles obtained by the dual-mode ring resonator is discussed. In addition, a filter design method based on this resonator is explained, followed by experimental results, which prove the validity of the proposed design method.


IEEE Transactions on Microwave Theory and Techniques | 1996

Stripline dual-mode ring resonators and their application to microwave devices

Hiroyuki Yabuki; Morikazu Sagawa; Michiaki Matsuo; Mitsuo Makimoto

This paper describes the fundamental properties of two orthogonal resonant modes within stripline ring resonators and their application to microwave devices. There are two principal methods for application of ring resonators, the first is by using two-port devices and the second four-port devices, in the case of two-port configurations, dual-mode filters using coupling between two degenerate modes have been studied as typical applications. In this paper, new methods for the coupling of two modes and their applications to practical devices, are proposed, and then experimental results for proof of the new structures are presented. Four-port configurations, which make use of two resonant modes as being independent or having no coupling between them, have a wider range of application to microwave devices. Microwave circuits such as tuned amplifiers and oscillators with novel structures are proposed, and their excellent characteristics are demonstrated. The experimental results obtained in this study on two and four-port devices make it clear that dual-mode ring resonators have great potential for application to various microwave devices.


IEEE Transactions on Microwave Theory and Techniques | 2001

Packaging using microelectromechanical technologies and planar components

Kazuaki Takahashi; Ushio Sangawa; Suguru Fujita; Michiaki Matsuo; Takeharu Urabe; Hiroshi Ogura; Hiroyuki Yabuki

A novel millimeter-wave packaging structure was developed in which a micromachined low-loss planar component and flip-chip devices were integrated on a silicon substrate. A low-loss planar filter was achieved on a 7-mm-square silicon substrate employing an inverted microstrip line and a unique resonator. High attenuation in the stopband was also obtained by introducing a pole control technique. Fabrication of a compact K-band receiver front-end incorporating a built-in filter was realized using multilayered benzocyclobutene (BCB) and flip-chip bonding techniques. Furthermore, we propose an alternative BCB suspended structure and demonstrate a planar antenna for Ka-band applications. These technologies bring to reality high-performance compact packaged systems in millimeter-wave region applications.


international microwave symposium | 2000

The design of a half-wavelength resonator BPF with attenuation poles at desired frequencies

Michiaki Matsuo; Hiroyuki Yabuki; Mitsuo Makimoto

A design method for a planar band-pass filter with attenuation poles based on a half-wavelength resonator is proposed. According to this design, the attenuation poles can be obtained at any desired frequency by means of coupling structures. Therefore, a filter with excellent attenuation characteristics for various applications can be achieved.


IEEE Transactions on Microwave Theory and Techniques | 2012

Analog Signal Processing for Pulse Compression Radar in 90-nm CMOS

Mehmet Parlak; Michiaki Matsuo; James F. Buckwalter

This paper presents a pulse-compression radar baseband analog signal processing integrated in a silicon process for low cost and power dissipation. The analog signal-processing circuitry exhibits the autocorrelation properties of the polyphase codes, maximizes the sensitivity and resolution of a pulse radar system, and alleviates speed and resolution requirements of the analog-to-digital converter (ADC) via an analog correlator. The circuitry includes a two-stage variable gain amplifier (VGA) for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. The differential 6-bit VGA is designed to adaptively track the Friis path loss through rapid change of the VGA gain and offset calibration, relaxing the dynamic range requirements of the correlator. The measured performance shows a VGA gain variation of 52 dB and a VGA group-delay imbalance of 50 ps over 64 states. The high-speed pulse compression/correlation is performed in analog current domain and the speed requirement on the ADC is reduced by a factor equal to the duty cycle lowering the ADC power consumption. The chip is fabricated in a 90-nm process, wire bonded on the FR4 printed circuit board, and tested with a Stratix IV field-programmable gate-array board to evaluate the system performance for different radar polyphase codes.


IEEE Transactions on Microwave Theory and Techniques | 2015

A Reconfigurable 50-Mb/s-1 Gb/s Pulse Compression Radar Signal Processor With Offset Calibration in 90-nm CMOS

Jun Li; Mehmet Parlak; Hirohito Mukai; Michiaki Matsuo; James F. Buckwalter

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution.


international microwave symposium | 1995

Miniaturized stripline dual-mode ring resonators and their application to oscillating devices

Hiroyuki Yabuki; Michiaki Matsuo; Morikazu Sagawa; Mitsuo Makimoto

Novel structures of miniaturized stripline Dual-Mode Resonators (DMRs) have been proposed, and their fundamental properties related to orthogonal modes are analytically derived. DMRs have attractive features which will provide many distinctive oscillating circuits. Experimental oscillating devices such as oscipliers and low phase noise voltage controlled oscillators using miniaturized DMRs are expected to have a practical use for various kinds of radio equipment in the RF and microwave regions. Moreover, this design concept is applicable for millimeter wave oscillators or smaller.<<ETX>>


ieee radar conference | 2011

Bidirectional circuitry for millimeter-wave pulse compression radar

Mehmet Parlak; James F. Buckwalter; Michiaki Matsuo

This paper discusses the monolithic integration of a bidirectional front-end and analog pre-processing circuits for pulse compression radar (PCR) system. The W-band front-end circuitry includes a bidirectional amplifier that operates as either an LNA or PA, a bidirectional analog phase shifter, and a double-balanced passive mixer. The baseband circuitry includes a two-stage VGA for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. Circuit simulations and measurement results for the front-end elements in a 0.12-µm SiGe BiCMOS process and circuit simulations of the baseband elements in a 90-nm CMOS process are presented.


custom integrated circuits conference | 2013

A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS

Jun Li; Hirohito Mukai; Mehmet Parlak; Michiaki Matsuo; James F. Buckwalter

This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal with the received signal. The circuit is fabricated in 90-nm CMOS and can be configured to work from 50Mb/s to 1Gb/s with Barker codes. A sidelobe reduction (SLR) of 15.6dB is demonstrated for 1Gb/s. The total power consumption is 33mW at 1Gb/s.


Archive | 2005

Radio communication device

Katsuaki Abe; Michiaki Matsuo; Noriaki Saito; Takenori Sakamoto; Akihiko Matsuoka

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