Michiel A. P. Pertijs

Precision temperature measurement using CMOS substrate pnp transistors

This paper analyzes the nonidealities of temperature sensors based on substrate pnp transistors and shows how their influence can be minimized. It focuses on temperature measurement using the difference between the base-emitter voltages of a transistor operated at two current densities. This difference is proportional to absolute temperature (PTAT). The effects of series resistance, current-gain variation, high-level injection, and the Early effect on the accuracy of this PTAT voltage are discussed. The results of measurements made on substrate pnp transistors in a standard 0.5-/spl mu/m CMOS process are presented to illustrate the effects of these nonidealities. It is shown that the modeling of the PTAT voltage can be improved by taking the temperature dependency of the effective emission coefficient into account using the reverse Early effect. With this refinement, the temperature can be extracted from the measurement data with an absolute accuracy of /spl plusmn/0.1/spl deg/C in the range of -50 to 130/spl deg/C.

An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation

This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrators output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping

This paper presents a precision general-purpose current-feedback instrumentation amplifier (CFIA) that employs a combination of ping-pong auto-zeroing and chopping to cancel its offset and 1/f noise. A comparison of offset-cancellation techniques shows that neither chopping nor auto-zeroing is an ideal solution for general-purpose CFIAs, since chopping results in output ripple, and auto-zeroing is associated with increased low-frequency noise. The presented CFIA mitigates these unintended side effects through a combination of these techniques. A ping-pong auto-zeroed input stage with slow-settling offset-nulling loops is applied to limit the bandwidth of the increased noise to less than half of the auto-zeroing frequency. This noise is then modulated away from DC by chopping the input stage at half the auto-zeroing frequency, reducing the low-frequency noise to the 27 nV/ white-noise level, without introducing extra output ripple. The auto-zeroing is augmented with settling phases to further reduce output transients. The CFIA was realized in a 0.5 μm analog CMOS process and achieves a typical offset of 2.8 μV and a CMRR of 140 dB in a common-mode voltage range that includes the negative supply.

A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications

This paper presents a fully integrated CMOS humidity sensor for a smart RFID sensor platform. The sensing element is a CMOS-compatible capacitive humidity sensor, which consists of top-metal finger-structure electrodes covered by a humidity-sensitive polyimide layer. Its humidity-sensitive capacitance is digitized by an energy-efficient capacitance-to-digital converter (CDC) based on a third-order delta-sigma modulator. This CDC employs current-efficient operational transconductance amplifiers based on current-starved cascoded inverters, whose limited output swing is accommodated by employing a feedforward loop-filter topology. A programmable offset capacitor is included to remove the sensors baseline capacitance and thus reduce the required dynamic range. To reduce offset errors due to charge injection of the switches, the entire system is auto-zeroed. The proposed humidity sensor has been realized in a 0.16- μm CMOS technology. Measurement results show that the CDC performs a 12.5-bit capacitance-to-digital conversion in a measurement time of 0.8 ms, while consuming only 8.6 μA from a 1.2-V supply. This corresponds to a state-of-the-art figure-of-merit of 1.4 pJ/conversion-step. Combined with the co-integrated humidity sensing element, it provides a resolution of 0.05% RH in the range from 30% RH to 100% RH while consuming only 8.3 nJ per measurement, which is an order-of-magnitude less energy than the state-of-the-art.

A high-accuracy temperature sensor with second-order curvature correction and digital bus interface

A high-accuracy CMOS temperature sensor with integrated bus interface is presented. It is shown that when offset cancellation and dynamic element matching techniques are applied, the accuracy of the sensor is mainly limited by process spread between batches on the substrate bipolar transistors. Therefore, the sensors can be calibrated per batch instead of per sensor. In combination with a second-order curvature correction technique, this results in a three-sigma accuracy of /spl plusmn/1.5/spl deg/C over the full temperature range.

Low-Power CMOS Smart Temperature Sensor With a Batch-Calibrated Inaccuracy of

In this paper, a low-power CMOS smart temperature sensor is presented. The temperature information extracted using substrate PNP transistors is digitized with a resolution of 0.03°C using a precision switched-capacitor (SC) incremental ΔΣ A/D converter. After batch calibration, an inaccuracy of ±0.25°C (±3) from -70°C to 130°C is obtained. This represents a two-fold improvement compared to the state-of-the-art. After individual calibration at room temperature, an inaccuracy better than ±0.1°C over the military temperature range is obtained, which is in-line with the state-of-the-art. This performance is achieved at a power consumption of 65 μW during a measurement time of 100 ms, by optimizing the power/inaccuracy tradeoffs, and by employing a clock frequency proportional to absolute temperature. The latter ensures accurate settling of the SC input stage at low temperatures, and reduces the effects of leakage currents at high temperatures.

{\pm}{0.25}^{\circ}{\rm C}~({\pm}3\sigma)

Smart temperature sensors generally need to be trimmed to obtain measurement errors below ±2°C. The associated temperature calibration procedure is time consuming and therefore costly. This paper presents two, much faster, voltage calibration techniques. Both make use of the fact that a voltage proportional to absolute temperature (PTAT) can be accurately generated on chip. By measuring this voltage, the sensors actual temperature can be determined, whereupon the sensor can be trimmed to correct for its dominant source of error: spread in the on-chip voltage reference. The first calibration technique consists of measuring the (small) PTAT voltage directly, while the second, more robust alternative does so indirectly, by using an external reference voltage and the on-chip ADC. Experimental results from a prototype fabricated in 0.7 ¿m CMOS technology show that after calibration and trimming, these two techniques result in measurement errors (±3¿) of ±0.15°C and ±0.25°C, respectively, in a range from -55°C to 125°C.

From

There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

{-}{70}^{\circ}{\rm C}

A major contributor to the total cost of precision CMOS temperature sensors is the cost of trimming and calibration. Significant cost savings can be obtained by batch calibration, but this is usually at the expense of an equally significant loss of accuracy [1]. This paper presents a CMOS temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from −70°C to 130°C, which represents a 2× improvement over the state of the art [2]. As in [2], individual trimming reduces the sensors inaccuracy to ±0.1°C (3σ) over the military range: −55°C to 125°C. The sensor draws 25µA from a 2.5V to 5.5V supply, which is significantly less than commercial products with comparable accuracy [3,4], and 3× less than the sensor reported in [2].

to 130

A smart temperature sensor in 0.7 /spl mu/m CMOS is accurate to within /spl plusmn/0.1/spl deg/C (3/spl sigma/) over the full military temperature range of -55/spl deg/C to 125/spl deg/C. The sensor uses substrate PNP transistors to measure temperature. Errors resulting from nonidealities in the readout circuitry are reduced to the 0.01/spl deg/C level. This is achieved by using dynamic element matching, a chopped current-gain independent PTAT bias circuit, and a low-offset second-order sigma-delta ADC that combines chopping and correlated double sampling. Spread of the base-emitter voltage characteristics of the substrate PNP transistors is compensated by trimming, based on a calibration at one temperature. A high trimming resolution is obtained by using a sigma-delta current DAC to fine-tune the bias current of the bipolar transistors.