Michiel Slotboom

Effect of the gap size on the SSI efficiency of split-gate memory cells

In this paper, new experimental results on the injection efficiency of split-gate memory cells programmed in the source-side-injection mode are reported. It is shown that the gap size has a negligible effect on the cell injection efficiency and, when the read current is not a limiting factor, it can be made large in order to increase the breakdown voltage of the oxide in the gap region, thus enhancing the cell reliability without detrimental effects on the performance. The experimental data is interpreted with the aid of fullband Monte Carlo simulations.

Performance and Reliability of 2-Transistor FN/FN Flash Arrays with Hafnium Based High-K Inter-Poly Dielectrics for Embedded NVM

Flash memories are difficult to embed in advanced CMOS generations, which is largely due to the nonscaling high program and erase (P/E) voltages; typically VPEap15V for cells operated by Fowler-Nordheim (FN) tunneling. Besides, for memories of only a few Mbytes, the need for these high voltages leads to a bad array-to-periphery area efficiency, resulting in a relatively large module size. Therefore, VPE reduction is an important driver for embedded flash scaling. Several flash-like technologies with lower P/E voltages have been explored over the past few years, e.g., nanocrystal and nitride memories. However, reliability, especially at high temperatures, is still an issue for these concepts. Therefore, in this work, we use the proven floating gate (FG) concept, but with the innovative approach of applying high-K materials in the inter-poly dielectric (IPD) between control gate (CG) and FG in order to increase the coupling ratio alphaCG, thus reducing VPE. The high-K IPD enables reduction of the equivalent oxide thickness (EOT) without compromising the data retention by leakage currents. To increase the (statistical) relevance of this work beyond that of single cell studies, we used full flash arrays

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.

Gate isolation technology for compact poly-CMP embedded flash memories

Downscaling the cell size of embedded flash memories is hampered by a minimum thickness of the tunnel oxide due to reliability constraints. The longer effective channel of the compact poly-CMP flash cell is beneficial for its scalability compared to a discrete two-transistor cell. This paper investigates the influence of the isolation spacer between the floating and access gates in the compact poly-CMP cell on read and leakage currents, programming and erasing characteristics and endurance. The effect of sidewall oxidation steps on the read current of the compact cell is also analysed. This has led to an improved scalable embedded compact poly-CMP flash cell aimed for the 90 nm CMOS generation and beyond.

Pushing the scaling limits of embedded non-volatile memories with high-K materials

In this paper, two alternative cell concepts to overcome these issues were discussed: conventional floating gate cells with high-K inter-poly dielectrics (IPD) and nitride trapping devices with high-K materials. In both concepts, the reduced equivalent oxide thickness (EOT) of the high-K layers helps reducing VPE, whereas the low leakage current ensures a good data retention. In this work, only hafnium based high-K materials were used: hafnium oxide (HfO2) and nitrided hafnium silicate (HfSiON), both deposited by MOCVD. The choice for these materials was based on their expected availability in the sub-45nm CMOS nodes

Compact poly-CMP embedded flash memory

Abstract In this paper, the compact poly-CMP cell concept is presented as a good candidate for scaled embedded flash memory in future mainstream CMOS technologies. In this compact cell concept the access gate is placed next to the stacked gate transistor. The access gate has a flat top surface due to the use of chemical mechanical polishing (CMP) and therefore no depth of focus problems with the exposure of the access gate mask occur. The feasibility is proven by electrical results on mini arrays in 0.25-μm CMOS technology. Both Fowler–Nordheim tunneling and source side injection programming is possible. The program and erase degradation is investigated by endurance cycling.

Self-aligned access gate technology for compact embedded flash memories

This paper investigates an approach to solve the access gate misalignment issues linked to the poly-CMP process of compact cells. The process of this self-aligned access gate approach is be detailed and measurements demonstrate the viability of this approach and show that the issues associated with access gate misalignment, such as parameter spread among cells during source side injection programming, are gone. This paves the way for aggressively scaled low power embedded nonvolatile memories for the next CMOS generations.

SPICE-Compatible Macro Model for Split-Gate Compact NVM Cell with Various Gap Sizes

In this paper we present a SPICE-compatible macro model based on three MOS transistors to describe split-gate non-volatile memory (NVM) cell characteristics for various sizes of the gap between the gates. The model has initially been developed based on simulated dc-IV-characteristics of reference cells (floating gate connected to control gate) and was verified later with measurements on reference as well as real floating gate cells.