Michinobu Nakao

Low overhead test point insertion for scan-based BIST

This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorithms, which are suitable for utilizing overhead reduction approaches such as restricted cell replacement, test point flip-flops sharing, are proposed to meet the above requirements. The effectiveness of the algorithms is demonstrated by some experiments.

Application of high-quality built-in test to industrial designs

This paper presents an approach for high-quality built-in test using a neighborhood pattern generator (NPG). The proposed NPG is practically acceptable because (a) its structure is independent of circuit under test, (b) it requires low area overhead and no performance degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

Accelerated test points selection method for scan-based BIST

This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).

Test generation for multiple-threshold gate-delay fault model

Presents a practical coverage metric in delay testing, which is called a multiple-threshold gate-delay fault model, to obtain high quality tests for large circuits. Fault efficiencies for given multiple thresholds of the delay fault size are computed, and their entirety describes the quality of tests. The approach guarantees that each gate-delay fault is not only robustly tested on almost the longest path, but also tested under the condition as a transition fault, by using two-pattern tests with a pattern-independent timing. We present procedures of path selection, fault simulation and test generation, where the path-status graph technique is used for an efficient computation. Experimental results for industrial circuits demonstrate that the proposed method can achieve high fault efficiencies for gate-delay faults having various fault sizes in a practical processing time.