Michio Morioka

Design and evaluation of the high performance multi-processor server

The paper discusses the architecture and performance of a prototype RISC multi-processor server designed for a business system like OLTP (online transaction processing). The combination of a low-latency cache-to-cache copy and an 8-way highly interleaved main memory realize high performance for the OLTP program. We analyzed the activity of the multi-processor system when executing the OLTP program by using the trace-driven simulator including kernel execution. The main findings are that: cache misses due to task migration and ping-ponging of kernel shared data occupy a larger part of the total misses, especially in a large cache capacity because of intensive I/O activities; and the low-latency cache-to-cache copy is very effective because 50-60% of the data read accesses are supplied by the cache-to-cache copy in a large cache capacity.<<ETX>>

Locally Differential Map Update Method with Maintained Road Connections for Telematics Services

Map databases for car navigation systems loaded with hard disk drives are rewritable. Thus, the ability to update map databases in such systems is expected. Furthermore, because telematics services are available through cell phones with reasonable costs, it is also becoming possible to download new information into car navigation systems anywhere. Hence, drivers want to update map databases in their terminals through telematics services. However, the volume of the entire map database is too large to be distributed through cell phones. Therefore, only changed data of the map database are distributed in differential map updates. However, even considering the reduction, the data size is still too large to distribute through cell phones. A Locally Differential Map Update (LDMU) is effective to reduce the data size, because with this method, a map is only partially updated. However, LDMU causes disconnection of the road network. Therefore, we propose Connection Maintained Locally Differential Map Update (CM-LDMU). This involves partially updating a map while maintaining the road network. In experiments with this method, less than 250 KB of data was required to update 20 times 20 km2 as wide as a medium-sized city. Thus, the feasibility of telematics map updating services is demonstrated.

Evaluation Of Memory System For Integrated Prolog Processor IPP

This paper discusses an optimal memory system to realize a high performance integrated Prolog processor, the IPP. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a micro instruction level. The main findings from this analysis are that: the write access ratio of Prolog is larger than that of procedural languages; and performance improvement requires the memory system to process concentrated, large write accesses effectively. Then the Prolog acceleration strategies for conventional cache memories are discussed. Comparison is made of cache memories (store-swap, store-through) and a stack buffer, regarding not only performance but also reliability, complexity and effects on procedural languages. The advanced store-through cache with a multi-stage write buffer and an interleaved main memory are seen to have the same performance level as the store-swap cache. When considering data reliability, the advanced store-through cache is judged more suitable for the IPP than the store-swap cache. In a comparison between stack buffer and advanced store-through cache, the stack buffer is found to achieve higher peak performance, but this is affected by the program features. On the other hand, the advanced store-through cache constantly gets high performance for Prolog and procedural languages. As a result, it is concluded that the advanced store-through cache is best suited to the IPP.