Miguel Recio

SmartBit/sup TM/: bitmap to defect correlation software for yield improvement

The need of higher yields on the wafer-manufacturing environment is pushing the yield analysts to develop new techniques and tools for yield improvement. With this scope, we present SmartBit/sup TM/, a software tool that provides detailed information about yield limiters by correlating bitmap to in-line defect data in an automatic mode, expediting the yield learning task. Based on the spatial correlation of bitmap data and the information of defects coming from the in-line inspections, SmartBit/sup TM/ provides a pareto where yield loss sources are separated and weighted by impact. SmartBit/sup TM/ also offers detailed information about the killer defects (defect class, origin, size, kill ratio and more) into a set of reports specially designed to obtain an overall view about the main problems affecting the fab yield. This is the key to fast and efficient yield learning. These reports are generated automatically using data from the full production of memory-products enhancing the reliability and completeness of the analysis.

Statistical bin analysis on wafer probe

In the semiconductor environment, statistical process control (SPC) has been extensively used to assure the quality of each fabrication step. The purpose of this paper is to show why and how the final step in integrated circuit (IC) manufacturing, the results from testing of all chips on each wafer, should be subject to statistical control as a standard operating procedure.

Knowledge-based software system for fast yield loss detection in a semiconductor fab

The comparative analysis of process machines in terms of yield related metrics (such as probe and E-Test data, process and particle data,. ..) is a source of a great deal of information for yield improvement. With this aim we published on SPIEs Microelectronic Manufacturing an Advanced Software System to detect machine-related yield limitors using a comparative analysis. This paper presents the natural expansion of that Software System by converting it into a more knowledge-based tool for fast yield loss detection on a semiconductor fab. The new System performs, in an automatic mode, the comparison among machines for every single step selected in the fabrication routing. The detection of statistically significative differences among machines at every step is performed using algorithms that incorporate the overall analysts experience on our fab. The output of the System allows a fast detection and reaction to yield issues, mainly to those that are still on the initial or baseline stages.

The 100% yield explanation approach in Lucent Technologies Madrid

A wealth of advantages arise from breaking down the overall yield into yield components that are easier to work and closer to the manufacturing line environment. We present in this paper our strategy to attempt the 100% yield explanation on our fab and the process of building a pareto that quantifies the impact of each yield component (defects, probe, nothing found, etc...). The most critical one, the defect related, is accounted by a set of knowledge-based automatic software tools that operate in our fab. They quantify it and break it down into the by layer, by defect size and type (ADC) contributions. The step forward of communication and deployment of this yield strategy is a key topic also discussed in the paper. On our way towards the 100% understanding of yield we have learned how to better manage it and taken advantage of many more opportunities to improve it. The strategy has shown to work both for new and mature technologies in our manufacturing line in Lucent Technologies Madrid.

STRATEGY AND TOOLS FOR YIELD ENHANCEMENT

We present an overview on yield enhancement in a semiconductor manufacturing environment. We discuss about the technical and strategic aspects of this field. On the technical side we deal with yield metrics definitions and yield analysis tools. The strategic side includes the work of quantifying and prioritize yield loss issues. Communication of yield to other organizations, that will be involved in the team work for the search of root cause identification and corrective and preventative action plans, is a key to a successful and sustained yield enhancement. The importance of moving from end-of-line yield enhancement standpoint to a more in-line view is also outlined.

Wafer level stress data successfully used as early burn-in predictor

We show that a simple post-stress test can provide a good early reliability indicator. The defect types that have been revealed by this post-stress test are two types of conductive particles on metal levels. This early indicator has been of great value when dealing with potentially contaminated wafers/lots and to evaluate and to prioritize the corrective actions to solve the line issues.

Wafer-level stress data successfully used as early burn-in predictor

We show that a simple post-stress test can provide a good early reliability indicator. The defect types that have been revealed by this post-stress test are two types of conductive particles on metal levels. This early indicator has been of great value when dealing with potentially contaminated wafers/lots and to evaluate and to prioritize the corrective actions to solve the line issues.

Toward 100% yield understanding approach in Lucent Technologies Madrid

A wealth of advantages arise form breaking down the overall yield into yield components that are easier to work and closer to the manufacturing line environment. We present in this paper our strategy to attempt the 100 percent yield explanation on our fab and the process of building a pareto that quantifies the impact of each yield component. The most critical one, the defect related, is accounted by a set of knowledge-based automatic software tools that operate in our fab. They quantify it and break it down into the by layer, by defect size and type contributions. The step forward of communication and deployment of this yield strategy is a key topic also discussed in the paper. On our way towards the 100 percent understanding of yield we have learned how to better manage it and taken advantage of many more opportunities to improve it. The strategy has shown to work both for new and mature technologies in our manufacturing line in Lucent Technologies Madrid.

Die allocation optimization for yield improvement

The way in which dies are allocated within a wafer is the subject of this paper. Standard ways of doing it are based on a software program, mainly in-house built, that uses default values for all the variables and do not take into account, in a direct mode, the actual distribution of yield versus distance to wafer edge in the manufacturing line where the chip is to be manufactured. We present a novel Software System for die allocation in the wafer, that uses an empirically obtained Yield Distribution Function (which gives the normalized yield for every X Y coordinate over the entire wafer area). The software developed gives as output the optimum die allocation in terms of yield.