Mihai Telescu

Fast communication: A simple algorithm for stable order reduction of z-domain Laguerre models

Discrete-time Laguerre series are a well known and efficient tool in system identification and modeling. This paper presents a simple solution for stable and accurate order reduction of systems described by a Laguerre model.

An application of Volterra series to IC buffer models

This paper presents a Volterra-based method of behavioral modeling for the I/O buffers of digital ICs. While this technique brings a slight improvement in accuracy over previous ones, its main strength is a greater degree of generality. With a modeling approach less dependent on the nature of the devices and more easily extendable to include the effects of multiple inputs one may hope better meet the challenges of advancing technology. The proposed models can be obtained from device port transient responses only and can be easily implemented in any simulation environment, including SPICE-based circuit description software. Two illustrative examples conclude the paper.

Statically constrained nonlinear models with application to IC buffers

Volterra series are well known approaches to modeling non-linear systems. In recent works a properly weighted combination of Volterra models have been used to successfully mimic the behavior of the output port of an integrated circuit buffer. The current paper focuses on a novel mechanism for controlling the static characteristic of such models. A commercial driver example is used to illustrate the efficiency of the technique to guarantee accurate static levels during time-domain simulations.

Low Complexity Equivalent Circuit Models for VLSI Interconnects

In this paper we present a technique for generating low complexity equivalent circuit models for VLSI circuit interconnects via the Laguerre-Gram model order reduction (MOR) method developed by our team. We discuss model passivity and equivalent circuit implementation and then show the advantages of our method in preserving important signal parameters such as rise time, delay and overshoot

Simplified topology for integrated circuit buffer behavioural models

This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this study provides a straightforward solution to modelling the input-output behaviour. Good model performance in overclocking conditions is an important advantage. This study also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.

Present and future of I/O-buffer behavioral macromodels

Modern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for system-level simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the state-of-the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed.

On the Use of Equality Constraints in the Identification of Volterra–Laguerre Models

This letter focuses on the a posteriori correction of Volterra-Laguerre models in order to meet specific static or dynamic requirements. The authors set a general theoretical framework and provide an illustrative example.

A Joint Linearization/Companding Approach for Improving a CO-OFDM Transmitter

The joint use of peak-to-average power ratio (PAPR) reduction and linearization via digital predistortion is investigated in this letter, with the view to improve the performances of coherent optical OFDM systems employing a semiconductor optical amplifier. The PAPR reduction is performed via Wangs nonlinear companding transform, which has been recently pointed out as a pertinent choice for optical communications, and a filter lookup table scheme is considered for linearizing the transmitter. Experimental results prove the effectiveness of the proposed scheme, as a lower error vector magnitude is achieved with respect to system implementations using only the PAPR reduction or linearization.

Fast communication: Efficient Gram-matrix computation for irrational resonant systems using Kautz models

We present a new method for evaluating the Gram matrix containing the inner products of repeated integrals and derivatives of irrational transfer functions via a Kautz model. The technique is particularly interesting for describing resonant systems and it has an immediate application in model order reduction.

Stable model order reduction method using Kautz functions: Application to VLSI circuits

In previous papers we presented MOR (model order reduction) methods based on the construction of a Gram matrix subsequent to a decomposition in Laguerre series. In this paper we propose an alternative solution using Kautz series, more adequate for modeling poorly damped systems.