Mihir R. Choudhury

Reliability Analysis of Logic Circuits

Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combinations, and correlations in gate failures. This paper presents three accurate and scalable algorithms for reliability analysis of logic circuits. The first algorithm, called observability-based reliability analysis, provides a closed-form expression for reliability and is accurate when single gate failures are dominant in a logic circuit. The second algorithm, called single-pass reliability analysis, computes reliability in a single topological walk through the logic circuit. It computes the exact reliability for circuits without reconvergent fan-out, even in the presence of multiple gate failures. The algorithm can also handle circuits with reconvergent fan-out with high accuracy using correlation coefficients as described in this paper. The third algorithm, called maximum- k gate failure reliability analysis, allows a constraint on the maximum number (k) of gates that can fail simultaneously in a logic circuit. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed algorithms.

TIMBER: time borrowing and error relaying for online timing error resilience

Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Two sequential circuit elements—TIMBER flip-flop and TIMBER latch—that implement error masking based on time-borrowing are described. Both circuit elements are validated using corner-case circuit simulations, and the overhead and trade-offs of TIMBER-based error masking are evaluated on an industrial processor.

Approximate logic circuits for low overhead, non-intrusive concurrent error detection

This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model - in posynomial form - is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual-VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach

Accurate and scalable reliability analysis of logic circuits

Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology alternatives. Reliability analysis of logic circuits is NP-hard because of the exponential number of inputs, combinations and correlations in gate failures, and their propagation and interaction at multiple primary outputs. By coupling probability theory with concepts from testing and logic synthesis, this paper presents accurate and scalable algorithms for reliability analysis of logic circuits. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed analysis technique.

Analytical model for TDDB-based performance degradation in combinational logic

With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred to as time-dependent dielectric breakdown (TDDB), is emerging as one of the most important sources of performance degradation in nanoscale CMOS devices. This paper describes an accurate analytical model to predict the delay of combinational logic gates subject to TDDB. The analytical model can be seamlessly integrated into a static timing analysis tool to analyze TDDB effects in large combinational logic circuits across a range of supply voltages and severity of oxide breakdown. Simulation results for an early version of an industrial 32nm library show that the model is accurate to within 3% of SPICE with orders of magnitude improvement in runtime.

Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability

Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics due to their excellent carrier-transport properties and potential for large-scale processing and fabrication. This paper combines atomistic quantum-transport modeling with circuit simulation to perform technology exploration for GNRFET circuits. Results indicate that GNRFETs offer significant gains over scaled CMOS at the 22-, 32-, and 45-nm nodes, with over 26-144× improvement in the energy-delay product at comparable operating points. A quantitative study of the effects of variations and defects on the performance and reliability of GNRFET circuits is also presented. Simulation results indicate that whereas GNRFET circuits promise higher performance, lower energy consumption, and comparable reliability at similar operating points to scaled CMOS circuits, they are more susceptible to variations and defects. These results motivate significant engineering, modeling, and simulation challenges facing the device and computer-aided design (CAD) communities involved in graphene electronics research.

Technology exploration for graphene nanoribbon FETs

Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale processing and fabrication. This paper combines atomistic quantum transport modeling with circuit simulation to perform technology exploration for GNRFET circuits. A quantitative study of the effects of variations and defects on the performance and reliability of GNRFET circuits is also presented. Simulation results indicate that whereas GNRFET circuits promise higher performance, lower energy consumption, and comparable reliability at similar operating points to scaled CMOS circuits, they are more susceptible to variations and defects. The results also motivate significant engineering, modeling, and simulation challenges facing the device and CAD communities involved in graphene electronics research.

Masking timing errors on speed-paths in logic circuits

There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low overhead solution for masking timing errors on speed-paths in logic circuits. Error masking at the outputs of a logic circuit is achieved by synthesis of a non-intrusive error-masking circuit that has at least 20% timing slack over the original logic circuit. The error-masking circuit can also be used to collect runtime information when the speed-paths are exercised to (i) predict the onset of wearout and (ii) assist in in-system silicon debug. Simulation results for several benchmark circuits and modules from the OpenSPARC T1 processor are presented to illustrate the effectiveness of the proposed solution. 100% masking of timing errors on all speed-paths within 10% of the critical path delay is achieved for all circuits with an average area (power) overhead of 16% (18%).

Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single- event upsets (SEUs) before they can be captured in latches/flip- flops. TTFs are tuned by adjusting the maximum width of the propagated SEU that can be suppressed. TTFs require 6-14 transistors, making them an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-VoD and gate sizing is described. Simulation results for the 70 nm process technology indicate that a 17-48X reduction in the soft error rate can be achieved with this approach.