Mikael Patel

A design representation for high level synthesis

TAO is a hierarchical graph representation of behaviour for high level synthesis of hardware structures. Typically a high level synthesis system takes a behavioural description and a set of constraints as input and generates a structural description of a hardware realization as output. One of the main questions when realizing an internal design representation is what data structures should be used to reduced time complexity of algorithms applied and how to organize these data structures. When using the TAO graph representation one must consider several types of graphs operations such as node merge and distribution. These require different representations to reduce the overall computational complexity of the procedure at hand. In this paper data structures for the three levels of TAO, task, algorithm, and operation graphs, are selected, defined, and discussed with examples of typical graph operations performed during the synthesis process from a behavioural towards a structural description.<<ETX>>

Good Practice and Improvement Model of Handling Capacity Requirements of Large Telecommunication Systems

There is evidence to suggest that the software industry has not yet matured as regards management of nonfunctional requirements (NFRs). Consequently the cost of achieving required quality is unnecessarily high. To try and avoid this, the telecommunication systems provider Ericsson defined a research task to try and improve the management of requirements for capacity, which is one of the most critical NFRs. Linkoping University joined in the effort and conducted an interview series to investigate good practice within different parts of the company. Inspired by the interviews and an ongoing process improvement project a model for improvement was created and activities were synthesized. This paper contributes the results from the interview series, and details the subprocesses of specification that should be improved. Such improvements are about understanding the relationship between numerical entities at all system levels, augmenting UML specifications to make NFRs visible, working with time budgets, and testing the sub system level components on the same level as they are specified

Extending the OpenUP/Basic Requirements Discipline to Specify Capacity Requirements

Software processes, such as RUP and agile methods, focus their requirements engineering part on use cases and thus functional requirements. Complex products, such as radio network control software, need special handling of non-functional requirements as well. We describe how we used the eclipse process framework to augment the open and minimal OpenUP/basic process with improvements found in management of capacity requirements in a case-study at Ericsson. The result is compared with another project improving RUP to handle performance requirements. The major differences between the improvements are that 1) they suggest a special, dedicated performance manager role and we suggest that present roles are augmented, 2) they suggest a bottom-up approach to performance verification while we focus on system performance first, i.e. top-down. Further, we suggest augmenting Um l-2 models with capacity attributes to improve information flow from requirements to implementation.

Integrating an improvement model of handling capacity requirements with the OpenUP/basic process

Contemporary software processes and modeling languages have a strong focus on Functional Requirements (FRs), whereas information of Non-Functional Requirements (NFRs) are managed with text-based documentation and individual skills of the personnel. In order to get a better understanding of how capacity requirements are handled, we carried out an interview series with various branches of Ericsson. The analysis of this material revealed 18 Capacity Sub-Processes (CSPs) that need to be attended to create a capacity-oriented development. In this paper we describe all these sub-processes and their mapping into an extension of the OpenUP/Basic software process. Such an extension will support a process engineer in realizing the sub-processes, and has at the same time shown that there are no internal inconsistencies of the CSPs. The extension provides a context for continued research in using UML to support negotiation between requirements and existing design.

Using observation and refinement to improve distributed systems test

Testing a distributed system is difficult. Good testing depends on both skill and understanding the system under test. We have developed a method to observe the system at the CORBA remote-procedure-call level and then use dynamic-query-based visualization to refine and improve the test cases. The method and accompanying tools have been tested and refined by using them as part of the software support effort for two distributed application, each having about 500 K lines of code. During this time the tools have been adapted to support testing by adding a scripting mechanism that permits the visualization tool to specify test reports. We also added parameter value observation and reporting. Finally, we added an active probing mechanism to induce faults and delays in order to stress the system under test. Our efforts have led to a substantial improvement in system test quality.

TAO: a hierarchical design representation for high level synthesis of hardware systems

Abstract The problem of synthesizing hardware structures from behavioural descriptions is recognized to be a hard task, with several levels of interacting sub-problems. In this paper a hierarchical graph based model of behaviour to support the traditional sub-problems in High Level Synthesis is presented. The main objective of this representation is to capture the different levels of parallelism available in a program, allow transformations to enhance the amount of parallelism, and reduce the size of the design search space so that an efficient and cost effective solution may be synthesized.

Random logic circuit implementation of extended Timed Petri Nets

Abstract Controller synthesis from high level specifications is one of the problem that has to be addressed to create Design Automation tools that will allow behaviour to structure level synthesis. This paper presents a method for realizing random logic circuit implementations of Timed Petri Nets. Timed Petri Nets have been shown to be effective methods of describing concurrent behaviour of hardware systems, and allows transformations to be applied to optimize a design specification given a set of constraints such as cost and time. The presented method of implementation requires delay free Timed Petri Nets, and a synchronous interpretation of the firing of transitions. The actual realization is achieves by first applying a one-to-one mapping to a generic hardware cell, and second reducing unnecessary gate logic through a set of simple transformation rules. Due to the direct mapping a fast method for cost and speed estimation is possible.

A case study in assessing and improving capacity using an anatomy of good practice

Capacity in telecommunication systems is highly related to operator revenue. As a vendor of such systems, Ericsson AB is continuously improving its processes for estimating, specifying, tuning, and testing the capacity of delivered systems. In order to systematize process improvements Ericsson AB and Linköping University joined forces to create an anatomy of Capacity Sub Processes (CSPs). The anatomy is the result of an interview series conducted to document good practices amongst organizations active in capacity improvement. In this paper we analyze four different development processes in terms of how far they have reached in their process maturity according to our anatomy and show possible improvement directions. Three of the processes are currently in use at Ericsson, and the fourth is the OpenUP/Basic process which we have used as a reference process in earlier research. We also include an analysis of the observed good practices. The result mainly confirms the order of CSPs in the anatomy, but we need to use our information of the maturity of products and the major life cycle in the organization in order to fully explain the role of the anatomy in planning of improvements.