Mikael Taveniku

Time-deterministic WDM star network for massively parallel computing in radar systems

In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and services to guarantee that deadlines are met. In this paper we analyze how these properties vary with the design parameters for a passive optical star network, specifically when used in a massively parallel radar signal processing system. The aggregated bandwidth and computational power of the radar system are approximately 45 Gb/s and 100 GOPS, respectively. The analysis is focused on the medium access control protocol, called TD-TWDMA, for the time and wavelength multiplexed network. It is concluded that the proposed network is very well suited to this kind of signal-processing applications. We also present a new distributed slot-allocation algorithm with real-time properties.

Estimating pressure peak position and air-fuel ratio using the ionization current and artificial neural networks

To optimize the performance and reduce the emission levels of an internal combustion engine one needs some measurements of the combustion process duality. We propose two artificial neural network models which use the ionization current for estimation of the position of the pressure peak and the air-fuel ratio. The pressure peak position model produces estimates on a cycle-by-cycle basis for each of the cylinders. These estimates are twice as good as estimates obtained from a linear model. The air-fuel ratio model uses the universal exhaust gas oxygen sensor as reference; it produces estimates that are ten times better than estimates obtained from a linear model.

Fiber-ribbon pipeline ring network for high-performance distributed computing systems

In this paper, we propose a high-bandwidth ring network built up with fiber-ribbon point-to-point links. The network has support for both packet switched and circuit switched traffic. Very high throughputs can be achieved in the network due to pipelining, i.e., several packets can be traveling through the network simultaneously but in different segments of the ring. The network can be built today using fiber-optic off-the-shelf components. The increasingly good price/performance ratio for fiber-ribbon links indicates a great success potential for the proposed kind of networks. We also present a massively parallel radar signal processing system with exceptionally high demands on the communication network. An aggregated throughput of tens of Gb/s is needed in this application, and this is achieved with the proposed network.

Using FPLs to Implement a Reconfigurable Highly Parallel Computer

With the arrival of large Field Programmable Gate Arrays (FPGAs) it is possible to build an entire computer using only FPGA and memory. In this paper we share some experience from building a highly parallel computer using this concept. Even if todays FPGAs are of considerable size, each processor must be relatively simple if a highly parallel computer is to be constructed from them. Based on our experience of other parallel computers and thorough studies of the intended applications, we think it is possible to build very powerful and efficient computers using bit-serial processing elements with SIMD (Single Instruction stream, Multiple Data streams) control.

Neural Virtual Sensors — Estimation of Combustion Quality in SI Engines using the Spark Plug

We propose two virtual sensors which estimate the location of the pressure peak and the air-fuel ratio from measurements of the ionization current across the spark plug gap.

A multiple SIMD approach to radar signal processing

Next generation radar systems, with phase-controlled array antennas, will have to process data that is many times larger than in current systems. This requires an enormous computing power. Even in a relatively small airborne radar system, with hard size and power consumption constraints, a sustained computing power of 40 GOPS (or 40 GFLOPS, if floating point calculations are used) will be needed to perform only the subset of the calculations known as the space-time adaptive processing (STAP). Consequently, there is a need for new parallel computing modules, as well as new overall system architectures and application development environments. In this paper a modular architecture with highly parallel SIMD-modules is presented as a promising solution, capable of handling STAP. A version of the architecture, equipped with bit-serial floating point processing elements, is described and evaluated. Implementation technology aspects are discussed.

The REMAP Reconfigurable Architecture : a Retrospective

The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture.