Mike Shuo-Wei Chen

Spectrum sharing radios

A major shift in radio design is now just beginning which attempts to share spectrum in a fundamentally new way. These radios are addressing the fact that spectrum is actually poorly utilized in many bands, in spite of the increasing demand for wireless connectivity. The new approaches to spectrum sharing make use of the advances in technology to implement new wireless systems that can share previously allocated spectra in such a way that the primary users of these spectra are not affected. Additionally, the allowed use of this band is on an unlicensed basis. Two methods that are being investigated to accomplish this task are the use of ultra wideband transmission and cognitive techniques. Ultra wideband transmission relies on the fact that if the bandwidth is increased, that reliable data transmission can occur even at power levels so low that primary radios in the same spectral bands are not affected. On the other hand the cognitive approach does not necessarily limit the transmission power, but rather attempts to share the spectra through a dynamic avoidance strategy. The opportunities and challenges of this new era in radio design are described along with the open questions in their implementation

A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

An 802.11n-draft-compliant 2times2, 2-stream MIMO radio SoC, incorporating two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface, has been integrated in a standard 0.13- mum digital CMOS technology with a die area of 36 mm2. The receiver achieves noise figures of 4 dB and 6 dB, respectively, at 2.4 GHz and 5 GHz. The transmitter EVM for a 2-stream, 40-MHz-bandwidth 64-QAM OFDM signal is - 31 dBc at 2.4 GHz and -8 dBm output power and -31.5 dBc at 5 GHz and - 4 dBm output power.

A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC

Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conventional analog charge-pump based PLLs [1–4]. This paper presents a calibration-free fractional-N DPLL that uses only an integer-N divider with a time-to-digital converter (TDC) embedded inside the VCO and utilizes a mismatch filtering technique to improve the linearity of the TDC.

Novel radio architectures for UWB, 60 GHz, and cognitive wireless systems

There are several new radio systems which exploit novel strategies being made possible by the regulatory agencies to increase the availability of spectrum for wireless applications. Three of these that will be discussed are ultra-wideband (UWB), 60 GHz, and cognitive radios. The UWB approach attempts to share the spectrum with higher-priority users by transmitting at power levels that are so low that they do not cause interference. On the other hand, cognitive radios attempt to share spectra by introducing a spectrum sensing function, so that they are able to transmit in unused portions at a given time, place, and frequency. Another approach is to exploit the advances in CMOS technology to operate in frequency bands in the millimeter-wave region. 60 GHz operation is particularly attractive because of the 7 GHz of unlicensed spectrum that has been made available there. In this paper, we present an overview of novel radio architecture design approaches and address challenges dealing with high-frequencies, wide-bandwidths, and large dynamic-range signals encountered in these future wireless systems.

Future wireless systems: UWB, 60GHz, and cognitive radios

There are a number of new radio systems which exploit novel strategies being made possible by the regulatory agencies to increase the availability of spectrum for wireless applications. Three of these that will be discussed are Ultra Wideband (UWS), 60 GHz and cognitive radios. The UWB approach attempts to share the spectrum with higher priority users by transmitting at power levels that are so low that they do not cause interference. On the other hand, Cognitive radios attempt to share spectra by introducing a spectrum sensing function, so that they are able to transmit in unused portions at a given time, place and frequency. Another approach is to exploit the advances in CMOS technology to operate in frequency bands in the millimeter wave region. 60 GHz operation is particularly attractive because of the 7 GHz of unlicensed spectrum that has been made available there

Cross-Layer Modeling and Simulation of Circuit Reliability

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

A subsampling UWB radio architecture by analytic signaling

This paper describes a signal processing technique which allows a reduction in the complexity of a transceiver for a 3.1-10.6 GHz ultra-wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency by subsampling, thus requiring substantially less hardware than a traditional narrowband approach. By exploring the properties of analytic signals, the system allows hardware reduction and a time resolution finer than the sampling period, which is useful for locationing or ranging applications.

A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.

A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling

SUMMARY This paper describes a system architecture along with signal processing technique which allows a reduction in the complexity of a 3.1–10.6 GHz Ultra-Wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end down-converts the signal frequency by subsampling, thus, requiring substantially less hardware than a traditional narrowband approach. However, the simplified receiver front end shows a high sensitivity to timing offset. By proposing an analytic signal processing technique, the vulnerability of timing offset is mitigated; furthermore, a time resolution finer than the sampling period is achieved, which is useful for locationing or ranging applications. Analysis and simulations of system specifications are also provided in this paper.

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band

A 12 bit Dual-Rate Hybrid digital-to-analog converter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows for high-speed third-order noise shaping with a digital standard cell design flow. The measured spurious-free dynamic range achieves 91-76 dB over the 500 MHz Nyquist band. The proposed DAC architecture is mostly digital and hence favors future technology scaling.