Mikio Mukai

Field effect transistor having multiple gate electrodes surrounding the channel region

Semiconductor memory cell and method of manufacturing the same

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Method of forming pattern

Semiconductor simulation method

Method of manufacturing a lateral field effect transistor

Method of manufacturing a Xmos insulated transistor

Joint structure for multilayer interconnections

Semiconductor memory cell and its fabrication process

Memory cell with stored charge on its gate and process for the manufacture thereof