Miloš Drutarovský

True Random Number Generator Embedded in Reconfigurable Hardware

This paper presents a new True Random Number Generator (TRNG) based on an analog Phase-Locked Loop (PLL) implemented in a digital Altera Field Programmable Logic Device (FPLD). Starting with an analysis of the one available on chip source of randomness - the PLL synthesized low jitter clock signal, a new simple and reliable method of true randomness extraction is proposed. Basic assumptions about statistical properties of jitter signal are confirmed by testing of mean value of the TRNG output signal. The quality of generated true random numbers is confirmed by passing standard NIST statistical tests. The described TRNG is tailored for embedded System-On-a-Programmable-Chip (SOPC) cryptographic applications and can provide a good quality true random bit-stream with throughput of several tens of kilobits per second. The possibility of including the proposed TRNG into a SOPC design significantly increases the system security of embedded cryptographic hardware.

Two Methods of Rijndael Implementation in Reconfigurable Hardware

This paper presents an evaluation of the Rijndael cipher, the Advanced Encryption Standard winner, from the viewpoint of its implementation in a Field Programmable Devices (FPD). Starting with an analysis of algorithms general characteristics a general cipher structure is described. Two different methods of Rijndael algorithm mapping to FPD are analyzed and suitability of available FPD families is evaluated. Finally, results of proposed mapping implemented in Altera FLEX, ACEX and APEX FPD are presented and compared with the fastest known Xilinx FPGA implementation. Results obtained are significantly faster than that of other implementations known up to now.

Efficient and Fast Method of Wall Parameter Estimation by Using UWB Radar System

Precise SAR imaging of objects or detection of moving a person behind a wall with UWB radar or nondestructive testing of walls in civil engineering requires the knowledge of wall parameters like thickness and permittivity. Their use in the data processing produces more precise and realistic results. The measurement of the wall parameters is challenge in a real environment especially when there is access only from one side of the wall. In this paper, an effective and fast algorithm for wall parameters estimation that can be used in practice is presented. For that purpose the magnitudes and the time positions of reflections from inner and outer interfaces of the wall are extracted from the data. A new scanning method reduces drastically the clutter caused by objects in the measurement environment such as reflections from other walls, the ceiling, the floor and antenna crosstalk. The algorithm was tested on 13 different types of walls with different permittivity and thickness. A handheld M-sequence UWB radar with horn and circular antennas was used for data gathering. The proposed method is very robust and the error of the thickness estimation was less than 10% for most of walls. The whole measurement can be handled by one person. The wall parameter estimation runs in real time and is fully automated.

High Performance True Random Number Generator in Altera Stratix FPLDs

The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, an on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry is used. In contrast with traditionally used free running oscillators, it uses and extends a recently developed method of randomness extraction based on two rationally related clock signals. Although it was developed for the Stratix family, the principle can be easily employed in other digital devices containing analog PLLs. We use the large flexibility of PLLs embedded in Stratix family to demonstrate the relationship between PLL and TRNG configuration, the quality of output random bit-stream, and the speed of the generator. The quality of TRNG output is confirmed by applying statistical tests, which pass also for a high-speed version of the generator giving up to 1M random bits per second. The generator developed for cryptographic applications helps to increase the system security, but it can also be used in a wide range of other applications.

Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware

We present an implementation of a simplified scalable architecture for the efficient realization of 3-D adaptive LUM smoother in the Field Programmable Logic Devices (FPLDs). The proposed filter architecture takes advantages of a combination of recently provided Boolean LUM smoothers with bit-serial realization of stack filters. In order to decrease hardware requirements, we implemented a highly reduced filter structure that is completely modular, scalable and optimized for hardware implementation in FPLD. Introduced simplifications significantly decrease a circuit complexity, however they still provide excellent smoothing capability and provide real-time performance for processing of 3-D signals with sampling frequencies up to 65 Msamples/ second.

Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study

This paper presents a case study of a hardware-software codesign of the RSA cipher embedded in reconfigurable hardware. The soft cores of Altera’s Nios RISC processor are used as the basic building block of the proposed complete embedded solutions. The effect of moving computationally intensive parts of RSA into an optimized parameterized scalable Montgomery coprocessor(s) is analyzed and compared with a pure software solution. The impact of the tasks distribution between the hardware and the software on the occupation of logic resources as well as the speed of the algorithm is demonstrated and generalized.

Short-range UWB radar: Surveillance robot equipment of the future

Autonomous robots are intelligent machines capable of performing tasks by themselves, without explicit human control. They can find quit a number of unique applications. Here, their utilisation for surveillance, monitoring and reconnaissance in hostile and dangerous to life environment intent on human being detection and/or static object imaging is up-to-date, promising and challenging as well. The fruitfulness of this application of robot systems is determined by many factors. The effective and reliable sensor system for human being detection and localization and static object imaging under wide variety of scenarios can be rated among them. In the last decade, it has been shown that ultra-wideband (UWB) radars (sensors) can be used with advantage as day and night, and under all-weather conditions sensors for person localization and static object imaging. Taking into account this fact, this paper will be intent on the analyses of UWB sensor applicability as the part of the smart sensor systems of robots to be used at emergency situation solutions. Summarizing the results of theoretical analyses and experiments with UWB sensors presented in the paper, it will be concluded that the short-range UWB radars have the great potential to be used as a standard equipment of surveillance and reconnaissance robot systems of future.

Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector

We present a Field Programmable Logic Devices (FPLDs) based implementation of a scalable filter architecture capable of detecting and removing impulsive noise in image sequences. The adaptive filter architecture is built using switching spatiotemporal filtering scheme and robust Lower-Upper-Middle (LUM) based noise detector. It uses highly optimized bit-serial pipelined implementation in Altera FPLDs. The proposed architecture provides real-time performance for 3-D image processing with sampling frequencies up to 97 Mpixels/second.