Ming-Yu Tsai

Para-CORDIC: parallel CORDIC rotation algorithm

In this paper, the parallel COrdinate Rotation DIgital Computer (CORDIC) rotation algorithm in circular and hyperbolic coordinate is proposed. The most critical path of the conventional CORDIC rotation lies in the determination of rotation directions, which depends on the sign of the remaining angle after each iteration. Using the binary-to-bipolar recoding (BBR) and microrotation angle recoding techniques, the rotation directions can be predicted directly from the binary value of the initial input angle. The original sequential CORDIC rotations can be divided into two phases where the rotations in each phase can be executed in parallel. Our proposed architectures have a more regular and simpler prediction scheme compared to previous approaches. The critical path delay is reduced since the concurrently predicted rotations can be combined using multioperand carry-save addition structures.

Improved Area-Efficient Weighted Modulo

In this brief, we proposed improved area-efficient weighted modulo 2n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n - 1} produced by existing diminished-1 modulo 2n + 1 adders. We have implemented the proposed adders using 0.13-¿m CMOS technology, and the area required for our adders is lesser than previously reported weighted modulo 2n + 1 adders with the same delay constraints.

2^{n} + 1

This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay.

Adder Design With Simple Correction Schemes

Exclusive-OR (XOR) gate is one of the critical components in many applications such as cryptography. In this paper, we present an efficient multi-input XOR circuit design based on pass-transistor logic (PTL). A synthesis algorithm is developed to efficiently generate the PTL-based multi-input XOR circuits. Both pre-layout and post-layout simulation results show that our proposed multi-input XOR design outperforms static CMOS design. The multi-input XOR circuits are also used to design the transformations in the Advanced Encryption Standard (AES).

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

A hybrid method of computing reciprocal is presented by combining the degree-two piecewise polynomial interpolation method and a Newton-Raphson iteration. The degree-two piecewise method is used to obtain an initial approximation for the subsequent Newton-Raphson operations. Architecture for the proposed hybrid method is designed considering the hardware sharing of the composing multipliers in the sub-word level, leading to significant improvement in area cost compared to conventional table-based designs and other hybrid approaches.

Automatic generation of high-performance multiple-input XOR/XNOR circuits and its application in Advanced Encryption Standard (AES)

We have designed pass-transistor logic (PTL)-based D flip-flop and T flip-flop to be used in finite field multiplication. Since both CMOS and PTL have their respective advantages in area, speed, and power, we have compared two different designs (conventional implementation and improved implementation) of serial-parallel finite field multiplication using pure CMOS, pure PTL, and hybrid PTL/CMOS logic. Experimental results with UMC 90nm technology show that the improved architecture of finite field multiplication composed of PTL-based T flip-flops can substantially reduce the total area, delay and power. Furthermore, the proposed cell-based design flow with hybrid PTL/CMOS cell library can be used to generate any other combinational and sequential logic circuits.

Low-cost design of reciprocal function units using shared multipliers and adders for polynomial approximation and Newton Raphson interpolation

In the past two decades, pass transistor logic has been shown to have smaller power and area cost compared to traditional CMOS logic for some applications. Some important issues related to the design of pass transistor cell library are discussed in this paper. First, the transistor sizing for the special inverter circuit in the cell library is addressed, which is quite different from the sizing of conventional CMOS inverter. Second, we create new cells that merge combinations of an inverters and some multiplexers in order to reduce the physical layout area. Experimental results show that the layout compaction method also reduces the delay and dynamic power. The proposed transistor sizing and layout compaction methods could be useful guidelines in designing the basic cells required in pass-transistor logic synthesis.

Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic

This paper presents a cell-based AISC design flow where the traditional CMOS cell library is replaced by pass-transistor logic (PTL) cell library. In particular, we develop an automatic PTL logic synthesizer to perform area-oriented synthesis by exploiting the characteristics of the PTL cell circuits. Two methods are used to reduce the area cost. The first method, called buffer elimination, for the pre-layout area minimization is to reduce the redundant inverters in the gate-level netlist during the logic mapping stage and results in an area saving of more than 50%. The second method, called layout compaction, is to reduce the layout area in the physical level by considering the design rules imposed on the PTL cell circuits, and lead to an additional 30% area saving.

Transistor sizing and layout merging of basic cells in pass transistor logic cell library

In this paper, we focus on the performance optimization of the final addition stage in a tree-structure multiplier. Two novel partitioning methods for the final addition are proposed in order to fully exploit the feature of nonuniform signal arrival time at different bit positions. Simulation results show that our methods have better performance compared to previous approaches.

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction

In a recent paper by Lin and Sheu, the authors have proposed a new circular-carry-selection technique that is applied in the design of an efficient diminished-one modulo 2n +1 adder. The proposed modulo adder in the aforementioned paper consists of a dual-sum carry look-ahead (DS-CLA) adder, a circular carry generator, and a multiplexer, which can reduce both area-time (AT) and time-power (TP) products compared with previous modulo adders. However, in our investigation, there will be incorrect results on the calculation of modulo addition because the carry-in of the DS-CLA adder is equal to zero. To remedy this drawback, we propose the corrected architecture of the DS-CLA adder based on the equations proposed in the aforementioned paper, which can perform correct modulo addition. The complexity of the corrected architecture is almost the same as the one proposed by Lin and Sheu but with less area cost, which can also have the same merits of both AT and TP products.