Mingyuan Xu

A 12 Bit 500MS/S SHA-less ADC in 0.18um CMOS

In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18pm CMOS process with 3.3V/1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz.

A clock duty cycle stabilizer based on DLL

Based on 0.18μm CMOS process, a clock duty cycle stabilizer is designed, which is suitable for high speed analog to digital converters (ADCs). The proposed circuit is improved from the traditional one: a new-type dynamic phase detector is used with simper construction and smaller power consumption, which eliminates the dead region which exists in the traditional phase detector; a kind of special delay cell is used to prevent false locking. The postlayout simulation shows that, working at 500MHz, the proposed clock stabling circuit can transform the duty cycle ranging from 10% or 90% to 50% with jitter smaller than 47fs, meeting the requirement of high speed ADCs.

A 12-Bit high-speed ADC based on GeSi BiCMOS process

In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, which isolates the ADC from external driver circuit, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages to achieve 12-bit accuracy. A double poly triple metal 0.35µm GeSi BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66dB and an SFDR of 80dB for sampling analog input frequencies up to 50MHz.

A 12-Bit 125MSPS ADC with capacitor mismatch trimming

In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35µm BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66dB and an SFDR of 80dB for sampling analog input frequencies up to 50MHz.