Mingzhi Dai

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

Flexible Low-Voltage Electric-Double-Layer TFTs Self-Assembled on Paper Substrates

Flexible low-voltage electric-double-layer (EDL) thin-film transistors (TFTs) with a patterned indium-tin-oxide (ITO) channel are self-assembled on paper substrates by only one shadow mask at room temperature. The operation voltage is 1.5 V when a microporous SiO2 solid electrolyte with large EDL capacitance is used as the gate dielectric. Such flexible TFTs operate in a full-depletion mode with a high mobility of 25.5 cm2/V · s, a low subthreshold swing of 0.16 V/decade, and a high current on/off ratio of 3 × 105. The influence of mechanical bending to the electrical performance of the flexible EDL TFTs is investigated. A device simulator is used to simulate the electrical behavior, and a nice fitting to the experimental data is obtained.

A Model With Temperature-Dependent Exponent for Hot-Carrier Injection in High-Voltage nMOSFETs Involving Hot-Hole Injection and Dispersion

An improved hot-hole-involved interface-state generation model is proposed for hot-carrier injection (HCI) degradation in high-voltage (HV) nMOSFETs. This model is based on experiments over a wide range of temperatures, voltage conditions, simulation results, and the underlying physical mechanisms. The model provides a thorough picture of an HCI system in HV nMOSFETs, with hot-hole injection related to an additional maximum electric-field region. The hot-hole injection in HCI is assumed to introduce deeper localized hydrogen states in gate-oxide films than that in negative-bias temperature instabilities. This result facilitates the dispersive transport of hydrogen. Therefore, HCI degradation in HV transistors is explained within the framework of disorder-controlled hydrogen kinetics. The power-law model can successfully predict temperature dependences for HCI degradation.

Modeling novel double-in-plane gate electric-double-layer thin-film and nanoscale transistors.

A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thin-film transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm(2)). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner.

Modeling of low-voltage oxide-based electric-double-layer thin-film transistors fabricated at room temperature

The room-temperature-made low-voltage electric-double-layer (EDL) thin-film transistors (TFTs) are reported previously with good performance including a huge EDL gate capacitance above 1 μF/cm2. We report a two-dimensional simulation of the carrier transport and subgap density of states (DOS) in low-voltage indium tin oxide EDL TFTs. The simple model with a constant mobility and two-step subgap DOS reproduces well the characteristics of EDL TFTs. A nice fitting to the experimental data was obtained with a changeable effective conduction band DOS and valence band DOS model, which is reasonable to EDL electrostatic modulation mechanism. The EDL TFTs show much lower DOS than the InGaZnO4 TFTs.

In-Plane-Gate Oxide-Based Thin-Film Transistors Self-Aligned on Stacked Self-Assembled Monolayer/

Low-voltage oxide-based thin-film transistors (TFTs) gated by stacked self-assembled octadecylphonic acid (ODPA) monolayer/SiO2 electrolyte with an in-plane-gate structure are self-aligned by one nickel shadow mask at room temperature. The stacked gate dielectrics show a reduced gate leakage current with the aid of the well-organized dense-stacked ODPA monolayer buffer. The equivalent field-effect mobility, subthreshold voltage swing, and drain current on/off ratio of such TFTs are estimated to be 11 cm2/V·s, 140 mV/dec, and 106, respectively. Such low-voltage in-plane-gate TFTs are very promising for low-cost portable sensors.

\hbox{SiO}_{2}

Sub-gap density of states (DOS) is a key parameter to impact the electrical characteristics of semiconductor materials-based transistors in integrated circuits. Previously, spectroscopy methodologies for DOS extractions include the static methods, temperature dependent spectroscopy and photonic spectroscopy. However, they might involve lots of assumptions, calculations, temperature or optical impacts into the intrinsic distribution of DOS along the bandgap of the materials. A direct and simpler method is developed to extract the DOS distribution from amorphous oxide-based thin-film transistors (TFTs) based on Dual gate pulse spectroscopy (GPS), introducing less extrinsic factors such as temperature and laborious numerical mathematical analysis than conventional methods. From this direct measurement, the sub-gap DOS distribution shows a peak value on the band-gap edge and in the order of 1017–1021/(cm3·eV), which is consistent with the previous results. The results could be described with the model involving both Gaussian and exponential components. This tool is useful as a diagnostics for the electrical properties of oxide materials and this study will benefit their modeling and improvement of the electrical properties and thus broaden their applications.

Electrolyte Dielectrics

Bottom-up nanowires are very attractive building blocks for functional devices due to their controllable properties. Meanwhile, assembling nanowires into large-scale integrated circuits is a daunting challenge because for the present circuits diverse nanowires are needed to grow simultaneously together closely. Here, a nanowire trigate transistor structure is proposed which can accomplish the functions of the logic gate circuits. By adding one channel-electrode junction as the output, this interesting one-channel structure is used to realize inverter and OR logic gates. In this way, logic circuits could shrink into a single transistor.

A Direct Method to Extract Transient Sub-Gap Density of State (DOS) Based on Dual Gate Pulse Spectroscopy

The effects of the channel thickness on the parameters used for subgap density of states (DOS) modeling for self-assembled oxide semiconductor based electric-double-layer (EDL) thin film transistors (TFTs) with high specific gate capacitance (>1 μF/cm2) were investigated. For indium-tin-oxide-based EDL TFTs, the channel current is affected by the channel thickness. The subgap DOS model with different parameters for different channel thicknesses, together with equations based on device physics, can explain such channel thickness dependence. Our study might lead to a better understanding of inorganic semiconductor EDL TFTs for improved device control.