Minjoong Rim

Lower-bound performance estimation for the high-level synthesis scheduling problem

A given behavioral specification can be implemented on a large number of register-transfer level designs. Instead of producing several designs and selecting the best one, synthesis systems may use estimation to reduce the design space. In this paper, we present a new technique for computing a lower-bound completion time for non-pipelined resource-constrained scheduling problem. Given a data flow graph, a set of resources, resource delays and a clock cycle, we derive a lower-bound on the completion time of a schedule. Our technique can handle chaining, multi-cycle operations and pipelined modules. The technique is very fast and experimental results show that it is also very tight. >

Optimal allocation and binding in high-level synthesis

The authors present an integer linear program (ILP) formulation for the allocation and binding problem in high-level synthesis. Given a behavioral specification and a time-step schedule of operations, the formulation minimizes wiring and multiplexer areas. An ILP model for minimizing multiplexer and wiring areas has been mathematically formulated and optimally solved. The model handles chaining, multi-cycle operations, pipelined modules, conditional branches and trades off wiring area with resource area.<<ETX>>

Global scheduling with code-motions for high-level synthesis applications

In this paper, we present a global scheduling technique for synthesis applications. The algorithm accepts a specification containing conditional branches and while-loop constructs and schedules it for a given set of resources. The algorithm performs several types of code motions across different basic blocks and trades off cost with performance. Several real-life examples taken from Numerical Recipes in C are used to demonstrate the efficacy of the approach. The results indicate that code-motions are very important for achieving significant speed-ups for synthesis applications. >

Representing conditional branches for high-level synthesis applications

The authors outline a new representation of behavioral specification for high-level synthesis applications. The main features of the representation are correct handling of conditional branches; the ability to tradeoff between control-select and data-select forms; keeping minimum necessary precedence relationships; correct representation of all conditional actions; and simplified mutual exclusion testing and correct determination of bit-widths and value transfers. The representation is simple and can be easily generated automatically.<<ETX>>

Optimal and heuristic algorithms for solving the binding problem

In this paper we present an optimal and a heuristic approach to solve the binding problem which occurs in high-level synthesis of digital systems. The optimal approach is based on an integer linear programming formulation. Given that such an approach is not practical for large problems, we then derive a heuristic from the ILP formulation which produces very good solutions in order of seconds. The heuristic is based on a network flow model and also considers floorplanning during the design process to minimize the interconnection area. >

Estimating lower-bound performance of schedules using a relaxation technique

A technique for computing a lower bound for nonpipelined resource-constrained scheduling performance is presented. Given a data-flow graph, a set of resources, resource delays, and clock cycle, a lower bound on the performance of a schedule is derived. The technique is fast (typical runtime of 50 ms), and the experimental lower-bounds are within two time steps of the actual schedules produced by a scheduling heuristic. The technique is also constructive and can be incorporated in a branch-and-bound method for solving the scheduling problem. The lower bound can be used to reduce a design search space. The method is applicable to lower-bound estimation in high-level synthesis.<<ETX>>

BINET: an algorithm for solving the binding problem

In this paper we present BINET (BInding using NETwork flows), a heuristic for solving the binding problem which occurs in high-level synthesis of digital systems. BINET is derived from an ILP formulation by mapping the binding problem for each time step onto a network optimization problem which can be optimally solved in polynomial time. Solving a sequence of these network flow problems gives a heuristic solution to the binding problem. BINET considers floorplanning during the design process and uses this information to reduce interconnect area. By using a rip-up and re-bind approach, considerable improvements can be achieved in the quality of the RTL design. BINET produces very good solutions in the order of seconds for several benchmarks. Among several current heuristics, BINET produces designs repairing minimum wiring requirement.<<ETX>>

Global Scheduling for High-Level Synthesis Applications

In this paper, we present a resource-constrained global scheduling technique for synthesis applications. The algorithm accepts specifications containing conditional branches and while loops and schedules them for a given set of resources. The algorithm performs several types of code motions across different basic blocks and trades off cost with performance. Several real-life examples are used to demonstrate the efficacy of the approach.

Valid Transformations: A New Class of Loop Transformations

In this paper we present a new class of loop optimizing transformations called valid transformations. This class of transformations are different from existing ones in that valid transformations can be illegal and can result in incorrect non-pipelined designs. Nevertheless, valid transformations have feasible pipeline schedules which is important for scheduling loops. We present an example valid transformation called loop expansion which can help explore a larger design space and helps in producing cost-performance efficient designs. Several examples are used to demonstrate the efficacy of the proposed transformations.

RECALS II: a new list scheduling algorithm

Presents a new scheduling heuristic RECALS II for high-level synthesis applications. RECALS II accepts a directed acyclic graph and a set of resources and schedules the graph while minimizing the number of clock cycles required to execute it. Experiments show that schedules produced by RECALS II are close to the optimal solutions.<<ETX>>