Minming Li

Rendezvous design algorithms for wireless sensor networks with a mobile base station

Recent research shows that significant energy saving can be achieved in wireless sensor networks with a mobile base station that collects data from sensor nodes via short-range communications. However, a major performance bottleneck of such WSNs is the significantly increased latency in data collection due to the low movement speed of mobile base stations. To address this issue, we propose a rendezvous-based data collection approach in which a subset of nodes serve as the rendezvous points that buffer and aggregate data originated from sources and transfer to the base station when it arrives. This approach combines the advantages of controlled mobility and in-network data caching and can achieve a desirable balance between network energy saving and data collection delay. We propose two efficient rendezvous design algorithms with provable performance bounds for mobile base stations with variable and fixed tracks, respectively. The effectiveness of our approach is validated through both theoretical analysis and extensive simulations.

Efficient Rendezvous Algorithms for Mobility-Enabled Wireless Sensor Networks

Recent research shows that significant energy saving can be achieved in mobility-enabled wireless sensor networks (WSNs) that visit sensor nodes and collect data from them via short-range communications. However, a major performance bottleneck of such WSNs is the significantly increased latency in data collection due to the low movement speed of mobile base stations. To address this issue, we propose a rendezvous-based data collection approach in which a subset of nodes serve as rendezvous points that buffer and aggregate data originated from sources and transfer to the base station when it arrives. This approach combines the advantages of controlled mobility and in-network data caching and can achieve a desirable balance between network energy saving and data collection delay. We propose efficient rendezvous design algorithms with provable performance bounds for mobile base stations with variable and fixed tracks, respectively. The effectiveness of our approach is validated through both theoretical analysis and extensive simulations.

TSP: thermal safe power: efficient power budgeting for many-core systems in dark silicon

Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The cooling solution is designed to dissipate this power level. But because TDP is not necessarily the maximum power that can be applied, chips are operated with Dynamic Thermal Management (DTM) techniques. To avoid excessive triggers of DTM, usually, system designers also use TDP as power constraint. However, using a single and constant value as power constraint, e.g., TDP, can result in big performance losses in many-core systems. Having better power budgeting techniques is a major step towards dealing with the dark silicon problem. This paper presents a new power budget concept, called Thermal Safe Power (TSP), which is an abstraction that provides safe power constraint values as a function of the number of simultaneously operating cores. Executing cores at any power consumption below TSP ensures that DTM is not triggered. TSP can be computed offline for the worst cases, or online for a particular mapping of cores. Our simulations show that using TSP as power constraint results in 50.5% and 14.2% higher average performance, compared to using constant power budgets (both per-chip and per-core) and a boosting technique, respectively. Moreover, TSP results in dark silicon estimations which are more optimistic than estimations using constant power budgets.

Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory

Phase change random access memory (PRAM) is one kind of nonvolatile memory, which is desirable to be used for DSP systems as main memory, as it consumes less power than DRAM and is much denser than DRAM. In this paper, we utilize a hybrid main memory composed of DRAM and PRAM, which leverages the low power consumption of PRAM while minimizing the performance and lifetime degradation caused by PRAM write. To make full use of different advantages of DRAM and PRAM, especially for the application-specific DSP systems, we reconsider the variable partitioning and instruction scheduling problems on the hybrid main memory. Different optimization objectives, for example power consumption, schedule length, and the number of writes on PRAM, are considered. At the same time, different kinds of hybrid architectures are analyzed. Graph models, ILP model, and algorithms are proposed for different settings. Experiments show that the proposed techniques reduce up to 49% power consumption and 88% the number of writes on PRAM on average.

Min-energy voltage allocation for tree-structured tasks

We study job scheduling on processors capable of running at variable voltage/speed to minimize energy consumption. Each job in a problem instance is specified by its arrival time and deadline, together with required number of CPU cycles. It is known that the minimum energy schedule for n jobs can be computed in O(n3) time, assuming a convex energy function. We investigate more efficient algorithms for computing the optimal schedule when the job sets have certain special structures. When the time intervals are structured as trees, the minimum energy schedule is shown to have a succinct characterization and is computable in time O(P) where P is the tree’s total path length. We also study an on-line average-rate heuristics AVR and prove that its energy consumption achieves a small constant competitive ratio for nested job sets and for job sets with limited overlap. Some simulation results are also given.

Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking

Cache is effective in bridging the gap between processor and memory speed. It is also a source of unpredictability because of its dynamic and adaptive behavior. Worst-case execution time (WCET) of an application is one of the most important criteria for real-time embedded system design. The unpredictability of instruction miss/hit behavior in the instruction cache (I-Cache) leads to an unnecessary over-estimation of the real-time applications WCET. A lot of modern processors provide cache locking capability. Static I-Cache locking locks function/instruction blocks of a program into the I-Cache before program execution. In this way, a more precise estimation of WCET can be achieved. The selection of functions/instructions to be locked in the I-Cache has dramatic influence on the performance of the real-time application. This paper focuses on the static I-Cache locking problem to minimize WCET for real-time embedded systems. We formulate the problem using an Execution Flow Tree (EFT) and a linear programming model. For a subset of the problems with certain properties, corresponding polynomial time optimal algorithms are proposed. We prove that the general problem is an NP-Hard problem. We also show that for a subset of the general problem with certain patterns, optimal solutions can be achieved in polynomial time. Experimental results show that our algorithms can reduce the WCET of applications further compared to current best known techniques.

Tighter Approximation Bounds for Minimum CDS in Wireless Ad Hoc Networks

Connected dominating set (CDS) has a wide range of applications in wireless ad hoc networks. A number of approximation algorithms for constructing a small CDS in wireless ad hoc networks have been proposed in the literature. The majority of these algorithms follow a general two-phased approach. The first phase constructs a dominating set, and the second phase selects additional nodes to interconnect the nodes in the dominating set. In the performance analyses of these two-phased algorithms, the relation between the independence number ? and the connected domination number ? c of a unit-disk graph plays the key role. The best-known relation between them is

Exploiting Statistical Mobility Models for Efficient Wi-Fi Deployment

\alpha\leq3\frac{2}{3}\gamma_{c}+1

Min-Energy Voltage Allocation for Tree-Structured Tasks

. In this paper, we prove that ? ≤ 3.4306? c + 4.8185. This relation leads to tighter upper bounds on the approximation ratios of two approximation algorithms proposed in the literature.

Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC

Recent years have witnessed the emergence of numerous new Internet services for mobile users. Supporting mobile applications through public Wi-Fi networks has received significant research attention. Nevertheless, recent empirical studies have shown that unplanned Wi-Fi networks cannot provide satisfactory quality of service (QoS) for interactive mobile applications because of intermittent network connectivity. In this paper, we exploit statistical mobility characteristics of users to deploy Wi-Fi Access Points (APs) for continuous service for mobile users. We study two AP deployment problems that aim at maximizing the continuous user coverage and minimizing the AP deployment cost, respectively. Both problems are formulated based on mobility graphs that capture the statistical mobility patterns of users. We prove that both problems are not only NP-complete but are identical to each other as well. We develop several optimal and approximation algorithms for different topologies of mobility graphs. We prove that our approximation algorithms generate the result that is at least half of the optimal solution. The effectiveness of our approaches is validated by extensive simulations using real user mobility traces.