Minsoo Ryu

Visual assessment of a real-time system design: a case study on a CNC controller

We describe our experiments on a real-time system design, focusing on design alternatives such as scheduling jitter, sensor-to-output latency, intertask communication schemes and the system utilization. The prime objective of these experiments was to evaluate a real-time design produced using the period calibration method (Gerber et al., 1995) and thus identify the limitations of the method. We chose a computerized numerical control (CNC) machine as our target real-time system and built a realistic controller and a plant simulator. Our results were extracted from a controlled series of more than a hundred test controllers obtained by varying four test variables. This study unveils many interesting facts: average sensor-to-output latency is one of the most dominating factors in determining control quality; the effect of scheduling jitter appears only when the average sensor-to-output latency is sufficiently small; and loop processing periods are another dominating factor of performance. Based on these results, we propose a new communication scheme and a new objective function for the period calibration method.

Streamlining real-time controller design: From performance specifications to end-to-end timing constraints

This paper presents a control theoretic approach to optimizing end-to-end timing constraints subject to the performance requirements and the schedulability constraint of a real-time control system. The control performance is specified in terms of control output responses such as steady state error maximum overshoot, settling time, and rise time; and the end-to-end timing constraints include loop processing periods and input-to-output latency. Our approach includes a generic real-time controller model on which our analysis is performed, and a heuristic optimization algorithm which derives end-to-end timing constraints. We apply the approach to the design of an embedded real-time controller and validate it through an experimental study using simulation. Our approach contributes to both the control and real-time areas: (1) it allows control engineers to take into consideration the effect of scheduling latency and sampling periods at the early stage of system design; and (2) it makes it possible to streamline the design of real-time control systems, since temporal requirements are derived in an automatic manner. Our approach can be effectively used with the period calibration method as its front-end.

Experimental Assessment of the Period Calibration Method: A Case Study

In this paper we present an experimental evaluation of the period calibration method (PCM) which was developed in Gerber et al. (1994, 1995) as a systematic design methodology for real-time systems. The objective of this experimental study is to assess design alternatives integrated into the method and their performance implication on resultant systems built via the PCM. Such design alternatives include scheduling jitter, sensor-to-output latency, intertask communication schemes, and system utilization. For this study, we have chosen a computerized numerical control (CNC) machine as our target real-time system, and built a realistic controller and a plant simulator. We show the detailed development process of the CNC controller and report its performance. The performance results were extracted from a controlled series of more than hundred test controllers obtained by varying four test variables. This study unveils several weaknesses of the PCM: (1) the communication scheme built into PCM incurs a large latency though average sensor-to-output latency is one of the most dominating factors in determining control quality; (2) scheduling jitter is taken seriously in PCM though its effect appears only when average sensor-to-output latency is sufficiently small; (3) loop processing periods are not properly optimized for control quality though they are another dominating factor of performance; and (4) transient overloads are not considered at all in PCM, even though they can seriously damage the performance of a system. Based on these results, we propose a new communication scheme and a transient overload handling technique for the improved period calibration method.

A Period Assignment Algorithm for Real-Time System Design

Digital controllers found in many industrial real-time systems consist of a number of interacting periodic tasks. To sustain the required control quality, these tasks possess the maximum activation periods as performance constraints. An essential step in developing a real-time system is thus to assign each of these tasks a constant period such that the maximum activation requirements are met while the system utilization is minimized [3]. Given a task graph design allowing producer/consumer relationships among tasks [4], resource demands of tasks, and range constraints on periods, the period assignment problem falls into a class of nonlinear optimization problems. This paper proposes a polynomial time approximation algorithm which produces a solution whose utilization does not exceed twice the optimal utilization. Our experimental analysis shows that the proposed algorithm finds solutions which are very close to the optimal ones in most cases of practical interest.

End-to-end design of distributed real-time systems

Abstract This paper presents a systematic approach to the design of distributed real-time systems with system-level timing requirements. It is often extremely difficult to design such a system in a composable fashion, since temporal relationships induced by system-level timing requirements introduce complicated couplings between structurally irrelevant components. As a solution to this problem, the approach described here maps system-level timing requirements onto component-level timing constraints. More specifically, it first transforms system-level requirements into a set of non-linear intermediate constraints; and then derives task attributes such as periods, phases, and deadlines, with the objective of maximizing the chances of the system being schedulable. The final results preserve the desired timing correctness: if the final task set is schedulable, then the original system-level requirements will be satisfied. The approach is demonstrated and experimentally validated via an example of a numerical control system built on the FIP network.

An effective design of master-slave operating system architecture for multiprocessor embedded systems

In this paper, we explore the problem of designing an effective master-slave operating system architecture for multiprocessors and describe current status of our prototype implementation, called APRIX (Asymmetric Parallel Real-tIme KernelS). This work has been largely motivated by the recent emergence of heterogeneous multiprocessors and the fact that the masterslave approach can be easily applied to heterogeneous multiprocessors while SMP (symmetric multiprocessing) approaches are restricted to homogeneous multiprocessors with UMA (Uniform Memory Access). The purpose of this paper is to identify and discuss design issues that have significant impact on the functionality and performance of the master-slave approach. Specifically, our study will investigate three major issues: structural design of a master-slave operating system based on our experience with a prototype development of APRIX, functional design of remote invocation mechanism that is required for executing kernel mode operations on a remote procesor, and performance improvement via application-specific kernel configuration. We finally describe our initial implementation of APRIX and preliminary experiment results.

RT-replayer: a record-replay architecture for embedded real-time software debugging

Recent embedded real-time software tends to be multithreaded and constrained by stringent timing requirements, thus often leading to serious faults depending on the precise timing of thread executions and event occurrences. A promising approach to debugging such complicated software is to log appropriate events during runtime and replay the same software execution based on them. This would allow one to effectively reproduce and track down the sources of faults. Unfortunately, previous software-based replayers have not paid much attention to the precise timing of software execution, but largely focused on the relative order of software events. Although some hardware-based replayers can provide such precise timing, they generally require a significant cost and are not available in usual development environments. In this paper, we present a software-based replayer, called RT-Replayer. RT-Replayer is based on two simple but effective software techniques, called virtual timestamps and instruction hooking, which enable faithful reproduction of the original software execution at instruction level accuracy.

Timing constraint remapping to achieve time equi-continuity in distributed real-time systems

Discretely synchronized, distributed real-time systems may suffer from a time discontinuity problem in that local clocks observe the disappearance or reappearance of time intervals. This problem occurs since traditional discrete clock synchronization algorithms adjust local clocks instantaneously. Such time discontinuities may lead to runtime faults due to the loss or gain of critical time points such as task release times and deadlines. In this paper, we propose a dynamic constraint transformation technique we call a constraint transformation for equi-continuity (CTEC) to correctly enforce timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much runtime overhead to be implemented in software. The proposed CTEC technique can solve the time discontinuity problem without modifying discrete clock synchronization algorithms. The CTEC, working as an added component of discrete clock synchronization, moves timing constraints out of discontinuous time intervals. In doing so, it makes use of a mapping derived from continuous clock synchronization in order to exploit its continuity property. We formally prove the correctness of CTEC by showing that the CTEC with discrete clock synchronization generates the same task schedule as continuous clock synchronization. In order to show the effectiveness of CTEC, we have implemented it on a distributed platform based on the CAN bus and performed extensive experiments. The experimental results indicate that time discontinuities present a consistency problem to real-world systems. They also show that CTEC is an effective solution to the problem while incurring little run-tine overhead.

Link-based similarity measures using reachability vectors.

We present a novel approach for computing link-based similarities among objects accurately by utilizing the link information pertaining to the objects involved. We discuss the problems with previous link-based similarity measures and propose a novel approach for computing link based similarities that does not suffer from these problems. In the proposed approach each target object is represented by a vector. Each element of the vector corresponds to all the objects in the given data, and the value of each element denotes the weight for the corresponding object. As for this weight value, we propose to utilize the probability of reaching from the target object to the specific object, computed using the “Random Walk with Restart” strategy. Then, we define the similarity between two objects as the cosine similarity of the two vectors. In this paper, we provide examples to show that our approach does not suffer from the aforementioned problems. We also evaluate the performance of the proposed methods in comparison with existing link-based measures, qualitatively and quantitatively, with respect to two kinds of data sets, scientific papers and Web documents. Our experimental results indicate that the proposed methods significantly outperform the existing measures.

Performance re-engineering of embedded real-time systems

This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new real-time throughput requirement specified as a systems period constraint.The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements. Since this approach does not modify carefully designed software structures, it helps reduce the reengineering cycle.