Miroslav N. Velev

Exploiting hierarchy and structure to efficiently solve graph coloring as SAT

Many important EDA problems can be formulated as graph coloring, which is a class of the Constraint Satisfaction Problem (CSP). This paper makes three contributions First, we define new encodings for representing CSPs as equivalent Boolean Satisfiability (SAT) problems: (1) a generalization of the log encoding by using ITE trees to select the domain values of a CSP variable, so that only conflict clauses are required; and (2) a simplified direct encoding, derived from the direct encoding (Where each domain value of a CSP variable is indexed by a unique Boolean variable) by omitting one of the Boolean variables and the at-least-one clause. Second, we propose the use of hierarchical encodings that combine several simple encodings to index the domain values of CSP variables, in order to produce SAT formulas that depend on fewer Boolean variables and are easier to solve. Third, we study schemes for static ordering of the Boolean variables in a Conjunctive Normal Form (CNF) representation of a CSP, based on the structure of the CSP graph, such that the resulting variable order is used for the decisions made by a SAT solver when evaluating the CNF. We compare 12 previously known SAT encodings for CSP with the two new encodings, as well as with 10 hybrid encodings. With symmetry-breaking constraints enforced, static variable ordering produced up to 2 orders of magnitude speedup. Additionally exploiting hierarchical encodings resulted in another order of magnitude speedup.

Comparison of Boolean satisfiability encodings on FPGA detailed routing problems

We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean satisfiability (SAT) problems against the only 2 previously used encodings. We also consider two symmetry-breaking heuristics. Compared to other methods for FPGA detailed routing, SAT-based approaches have the advantage that they can prove the unroutability of a global routing for a particular number of tracks per channel, and that they consider all nets simultaneously. The experiments were run on the standard MCNC benchmarks. The combination of one new encoding with a new symmetry-breaking heuristic resulted in speedup of 3 orders of magnitude or 1,139x of the total execution time on the collection of benchmarks, when proving the unroutability of FPGA global routings. The maximum obtained speedup was 9,499x on an individual benchmark. On the other hand, most of the encodings had comparable and very efficient performance when finding solutions for configurations that were routable. The availability of many SAT encodings, that can each be combined with various symmetry-breaking heuristics, opens the possibility to design portfolios of parallel strategies - each a combination of a SAT encoding and a symmetry- breaking heuristic - that can be run in parallel on different cores of a multicore CPU in order to reduce the solution time, with the rest of the runs terminated as soon as one of them returns an answer. We found that a portfolio of three particular parallel strategies produced additional speedup of more than 2x.

A method for debugging of pipelined processors in formal verification by correspondence checking

Presented is a method for debugging of pipelined processors in their formal verification with the highly automatic and scalable approach of Correspondence Checking, where a pipelined/superscalar/VLIW implementation is compared against a non-pipelined specification via an inductive correctness criterion based on symbolic simulation in a way that guarantees the correctness of the implementation for all possible execution scenarios. The benefit from the proposed method increases with the complexity of the processor under formal verification. For a 12-stage VLIW processor that imitates the Intel Itanium in many features, the method reduced the size of the EUFM correctness formulas from buggy processors by up to an order of magnitude, the number of Boolean variables in the equivalent propositional correctness formulas and the number of 1s in the counterexample traces by up to 2 orders of magnitude, and resulted in an average speedup in detecting the bugs of 2 orders of magnitude, thus increasing the productivity of the processor designers.

Application of Hierarchical Hybrid Encodings to Efficient Translation of CSPs to SAT

Solving Constraint Satisfaction Problems (CSPs) through Boolean Satisfiability (SAT) requires suitable encodings for translating CSPs to equivalent SAT instances that can not only be efficiently generated, but also efficiently solved by SAT solvers. In this paper we investigate hierarchical and hybrid encodings, as proposed by Velev, namely a previously studied log-direct encoding, and a new combination, the log-order encoding. Experiments on different domain problems with these hierarchical encodings demonstrate their significant promise in practice. Our experiments show that the log-direct encoding significantly outperforms the direct encoding (typically by one or two orders of magnitude) taking advantage not only of the more concise representation, but also of the better capability of the log-direct encoding to represent interval variables. We also show that the log-order encoding is competitive with the order encoding, although more studies are required to understand the tradeoff between the fewer variables and longer clauses in the former, when expressing complex CSP constraints.

Automatic formal verification of multithreaded pipelined microprocessors

We present highly automatic techniques for formal verification of pipelined microprocessors with hardware support for multithreading. The processors are modeled at a high level of abstraction, using a subset of Verilog, in a way that allows us to exploit the property of Positive Equality that results in significant simplifications of the solution space, and orders of magnitude speedup relative to previous methods. We propose abstraction techniques that produce at least 3 orders of magnitude speedup, which is increasing with the number of threads implemented in a pipelined processor. To the best of our knowledge, this is the first work on automatic formal verification of pipelined processors with hardware support for multithreading.

Automated debugging of counterexamples in formal verification of pipelined microprocessors

We propose a novel method for error diagnosis of pipelined microprocessors that allows us to exploit Positive Equality in Correspondence Checking. We also present static CNF variable ordering heuristics that dramatically reduce the solution space during the debugging. Experimental results indicate speedup of up to 2 orders of magnitude relative to previous approaches when applying the method to automated debugging in formal verification of complex pipelined DSPs.

Automatic formal verification of reconfigurable DSPs

We present a method for automatic formal verification of Digital Signal Processors (DSPs) that have VLIW architecture and reconfigurable functional units optimized for accelerating Software Defined Radio (SDR) applications to be used for future space communications by NASA. The formal verification was done with the highly automatic method of Correspondence Checking by exploiting the property of Positive Equality that allows a dramatic simplification of the solution space and many orders of magnitude speedup. The formal verification of a complex reconfigurable DSP took approximately 10 minutes of CPU time on a single workstation, when using our industrial-strength tool flow.

Efficient SAT-based techniques for Design of Experiments by using static variable ordering

Design of Experiments (DOE) is an important problem for ensuring the quality of EDA with applications to the evaluation of techniques and tools in all sub-fields of EDA, e.g., yield and variability optimization, error correcting codes, and software testing. DOE can be formulated as a Quasigroup Completion Problem (QCP). We propose and compare 23 heuristics for efficient solving of QCPs by translation to Boolean Satisfiability (SAT) and exploiting static Boolean variable ordering to solve the resulting SAT formulas. This comparison is based on both satisfiable and unsatisfiable instances with varying numbers of empty cells. The translation to SAT is done with the minimal (2-D) and extended (3-D) encodings by Kautz et al. The contributions of the paper include: 1) proposal and comparison of the 23 heuristics; 2) study of the benefits from the 3-D vs. the 2-D encoding, and from local symmetry-breaking constraints, given the static variable ordering heuristics; and 3) identification of the most efficient single heuristic, and portfolios of heuristics that can be run in parallel on multiple cores in a modern CPU. Compared to the default dynamic variable ordering heuristic in the SAT solver, when using static variable-ordering heuristics we achieve an average speedup of 2.8× with the single best heuristic, 7.2× with the best portfolio of two parallel heuristics, 13.6× with the best portfolio of four parallel heuristics, and speedups on individual benchmarks of up to 3 orders of magnitude.

Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality

With the number of processor cores in modern CPUs growing exponentially, it is expected that CPUs will have on the order of a hundred cores in the next 5 – 7 years. Thus, the need to implement parallel SMT decision procedures to utilize the increasing number of cores. We study a method to design independent strategies for a portfolio of parallel independent strategies in an SMT decision procedure for the logic of Equality with Uninterpreted Functions and Memories (EUFM). Particularly, our goal is to complement the previously used relative encoding (also called eij encoding) and logarithmic encoding of equations by exploiting hierarchical encodings of equations. Hierarchical encodings can have a wide variety of structures, where each level of the hierarchy uses a different simple encoding, and thus the potential for many possible translations to SAT with such encodings. Hierarchical encodings produced a speedup of at least an order of magnitude for an out-of-order superscalar processor with issue/retire width of 14 instructions per clock cycle, such that the speedup increases with the complexity of the microprocessor under formal verification.

Efficient SAT Techniques for Relative Encoding of Permutations with Constraints

We present new techniques for relative SAT encoding of permutations with constraints, resulting in improved scalability compared to the previous approach by Prestwich, when applied to searching for Hamiltonian cycles. We observe that half of the ordering variables and two-thirds of the transitivity constraints can be eliminated. We exploit minimal enumeration of transitivity, based on 12 triangulation heuristics, and 11 heuristics for selecting the first node in the Hamiltonian cycle. We propose the use of inverse transitivity constraints. We achieve 3 orders of magnitude average speedup on satisfiable random graphs from the phase transition region, 2 orders of magnitude average speedup on unsatisfiable random graphs, and up to 4 orders of magnitude speedup on satisfiable structured graphs from the DIMACS graph coloring instances.