Mitchell A. Bauman

High-performance modular memory system with crossbar connections

Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues

Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed

System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same.

Address conflict detection system employing address indirection for use in a high-speed multi-processor system

System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions

Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks

High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems

Multi-processor data processing system with multiple second level caches mapable to all of addressable memory

System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency