Mitrajit Chatterjee

A novel pattern generator for near-perfect fault-coverage

A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The pattern generator consists of two components: a GLFSR, earlier proposed as a pseudo-random pattern generator, and combinational logic, to snap the outputs of the pseudo-random pattern generator. Using fewer test patterns with only a small area overhead, this combinatorial logic block, for a particular CUT, can be designed to achieve nearly 100% single stuck-at fault coverage. Specifically, where weighted pattern generators only enhance the probability of testing a specified set of hard-to-detect faults, the proposed combinational logic, using a comparable hardware overhead, can guarantee generating the test for those faults. Experimental results demonstrate that under identical conditions, the fault coverage of the proposed pattern generator is significantly higher, compared to the conventional weighted pattern generation techniques. For enhancing effectiveness, this combinational logic mapping technique can also be used to augment any weighted pattern technique. Because LFSRs are special cases of GLFSRs, our design is more general than LFSR-based designs.

GLFSR-a new test pattern generator for built-in-self-test

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. These are linear feedback shift registers (LFSRs) over a Galois field GF(2/sup /spl delta//), (/spl delta/>1). Unlike conventional LFSRs, which are over GF(2), these generators are not equivalent to cellular arrays and are shown to achieve significantly higher fault coverage. Experimental results are presented in this paper depicting that the proposed GLFSR can attain fault coverage equivalent to the LPSR, but with significantly fewer patterns. Specifically, results obtained demonstrate that in combinational circuits, for both stuck-at as well as transition faults, the proposed GLFSR outperforms all conventional pattern generators. Moreover, these experimental results are validated by certain randomness tests which demonstrate that the patterns generated by GLFSR achieve a higher degree of randomless.

LOT: logic optimization with testability—new transformations using recursive learning

A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tools like SIS and HANNIBAL.

VERILAT: verification using logic augmentation and transformations

This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is either not changed during the verification process, as in OBDD or implication-based methods, or the circuit is progressively reduced during verification. Whereas in our approach, we actually enlarge the circuits by adding gates during the verification process. Specifically introduced here is a new technique that transforms the reference circuit as well as the circuit to be verified, so that the similarity between the two is progressively enhanced. This requires addition of gates to the reference circuit and/or the circuit to be verified. In the process, we reduce the dissimilarity between the two circuits, which makes it easier to verify the circuits.

Gate-level synthesis for low-power using new transformations

A new logic optimization method of multi-level combinational CMOS circuits is presented, which minimizes both power as well as power dissipation per unit area. The method described here uses Boolean transformations which exploit implications at the gate-level, based on both controllability and observability relationships. New transformations which form the basis of our synthesis method are presented. The emphasis is on power consumption rather than on area. Experimental results demonstrate that circuits synthesized by our method consume less power with a comparable area than those synthesized by state-of-the-art tools.

Buffer assignment algorithms on data driven ASICs

Data driven architectures have significant potential in the design of high performance ASICs. By exploiting the inherent parallelism in the application, these architectures can maximize pipelining. The key consideration involved with the design of a data driven ASIC is ensuring that throughput is maximized while a relatively low area is maintained. Optimal throughput can be realized by ensuring that all operands arrive simultaneously at their corresponding operator node. If this condition is achieved, the underlying data flow graph is said to be balanced. If the initial data flow graph is unbalanced, buffers must be inserted to prevent the clogging of the pipeline along the shorter paths. A novel algorithm for the assignment of buffers in a data flow graph is proposed. The method can also be applied to achieve wave-pipelining in digital systems under certain restrictions. The algorithm uses a new application of the retiming technique; the number of buffers here is shown to be equal to the minimum number of buffers achieved by integer programming techniques. We also discuss an extension of this algorithm which can further reduce the number of buffers by altering the DFG without affecting functionality or performance. The time complexities of the proposed algorithms are O(V/spl times/E) and O(V/sup 2//spl times/logV), respectively, a considerable improvement over the existing strategies. Also proposed is a novel buffer distribution algorithm that exploits a unique feature of data driven operation. This procedure maximizes throughput by inserting substantially fewer buffers than other techniques. Experimental results show that the proposed algorithms outperform the existing methods.

Buffer assignment for data driven architectures

Data driven architectures have the potential to exhibit higher performance and throughput when compared to their control driven counterparts. In order to ensure that these performance gains are realized, it is required that the underlying data flow graph (DFG) have no accumulation of data at its nodes. Hence, all operands should arrive simultaneously at a multi-input operation node. Buffers are therefore inserted to ensure these conditions. An algorithm for buffer distribution in a balanced DFG of order (V /spl times/ E) is proposed. The number of buffers in the proposed buffer distribution strategy is equal to the minimum number of buffers achieved by integer programming techniques. An extension of this algorithm, of order (V/sup 2/ /spl times/ log V) is proposed which can further reduce the number of buffers by altering the DFG while keeping the functionality and performance of the DFG intact. Performance results showing the improvement of these algorithms over the existing ones have been shown.