Mitsuhiko Yagyu

Design of FIR digital filters with minimum weight representation

This paper proposes an algorithm for the iterative design of FIR digital filters whose coefficients have minimum weight representation. The total number of nonzero bits is limited. In each iteration the coefficient vector is up-dated so that some sets of the amplitude ripples become smaller. The direction is found by solving linear simultaneous equations. The method evaluates the normalized peak ripples in the minimax sense. Several examples show that the proposed method yields superior filter responses compared to the conventional methods.

Minimization of adders in fast FIR digital filters and its application to filter design

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartleys technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartleys technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

Design of linear phase FIR digital filters using minimal number of adders and subtractors

Linear phase FIR digital filters whose coefficients are expressed as canonic signed digit (CSD) code can be efficiently realized by using a small number of adders and subtractors instead of multipliers. Common uses of the adders and subtractors can further reduce the number of adders and subtractors (NAS). The use of additional adders and subtractors to recover the reduction can improve the frequency responses of those filters. An algorithm to optimize the frequency responses of such filters is proposed. Many examples confirm that, using the specified NAS, the obtained filters leave better frequency responses compared to the conventional CSD structures.

Stable single-bit noise-shaping quantizer based on data coding into optimized binary vectors

This paper presents data coding techniques for a stable single-bit noise-shaping quantizer, which has a cascade structure of a multi-bit /spl Sigma//spl Delta/ modulator (/spl Sigma//spl Delta/M) and a binary interpolator. The binary interpolator chooses a pre-optimized binary vector for each input sample and successively generates the chosen binary vector as an output binary sequence. The binary vectors can have different lengths. The paper also proposes two methods to evaluate and bound output errors of a binary interpolator. A multi-bit /spl Sigma//spl Delta/M is designed to cause no overload for all possible input signals whose amplitudes are bounded to a specified level, and thus the /spl Sigma//spl Delta/M rigorously guarantees the stability condition. In a design example, we have evaluated SNDRs and a noise spectrum and then confirmed that our stable quantizer can sharply shape output noise spectra.

Minimization of finite wordlength error in 2-D FIR digital filters in the frequency domain

This paper presents a method to minimize the finite wordlength error in output signals of linear phase 2-D FIR filters. The finite wordlength errors can be easily analyzed in the frequency domain when the input signal statistics are known. In the case of white input signals, impulse responses corresponding to all levels of input impulses are optimized so as to minimize the errors. A new ROM based filter structure is proposed in which the optimized impulse responses are stored in the ROM. The output signals are generated by superposing the impulse responses corresponding to the input levels. Many results of simulations confirm that the output signals of the proposed filters have far less errors than those of conventional filters.

Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation

This paper proposes hardware-efficient VLSI architectures for 2-channel signal word decomposed filters (2-ch SWDFs) and their design method in consideration of the implemented circuit size. By consideration of the circuit size in design method, 2-ch SWDFs with a minimum output error among SWDFs whose size is equal to or smaller than a specification can be designed. Canonical Signed Digit expressions are used to effectively represent the filter coefficients of the SWDFs in order to make its circuit size small. Through precise analysis of the internal structures, circuit size can be accurately estimated. Some design examples show that the proposed method can design filters whose output error is about -12 dB lower than that of the linear FIR filters. Compared to an exhaustive search method, our method is much faster and can design filters whose output errors are only about 2 dB more.

Analysis and minimization of finite wordlength error of FIR digital filters in the frequency domain

This paper presents a method to analyze and minimize finite wordlength errors in output signals of linear phase FIR filters. In the frequency domain, impulse responses corresponding to all levels of input impulses are optimized. If the probability densities of input signals are taken into account, the errors in the output signals of the filters are smaller than those in the conventional filters. For image signals, which have only positive values, the non-symmetry of their probability densities makes the proposed algorithm more effective. Many results of simulations confirm that the output signals of the proposed filters have far less errors than those of conventional filters.