Mitsuru Tomono

Real-Time Human Pose Estimation via Cascaded Neural Networks Embedded with Multi-task Learning

Deep convolutional neural networks (DCNNs) have recently been applied to Human pose estimation (HPE). However, most conventional methods have involved multiple models, and these models have been independently designed and optimized, which has led to sub-optimal performance. In addition, these methods based on multiple DCNNs have been computationally expensive and unsuitable for real-time applications. This paper proposes a novel end-to-end framework implemented with cascaded neural networks. Our proposed framework includes three tasks: (1) detecting regions which include parts of the human body, (2) predicting the coordinates of human body joints in the regions, and (3) finding optimum points as coordinates of human body joints. These three tasks are jointly optimized. Our experimental results demonstrated that our framework improved the accuracy and the running time was 2.57 times faster than conventional methods.

An energy-efficient SIMD DSP with multiple VLIW configurations and an advanced memory access unit for LTE-A modem LSIs

Energy efficiency is the most important factor in the design of wireless modem LSIs for mobile handset systems. We have developed an energy-efficient SIMD DSP for LTE-A modem LSIs. Our DSP has mainly two hardware features in order to reduce energy consumption. The first one is multiple VLIW configurations to minimize accesses to instruction memories. The second one is an advanced memory access unit to realize complex memory accesses required for wireless baseband processing. With these features, performance of our DSP is about 1.7 times faster than a base DSP on average for standard LTE-A Libraries. Our DSP achieves about 20% improvement in energy efficiency compared to a base DSP for LTE-A modem LSIs.

A novel processor design flow using processor description language applied to a vector coprocessor

We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an architecture design flow with an untimed model and a performance estimator. We achieved 4.5 times better design efficiency compared to a conventional implementation design flow with a timed model. As a result, we were able to reduce design and optimization time dramatically.