Mitsutoshi Yahara

A Study on Flash Type A/D Converter Using Neuron CMOS Inverter

In this paper, we propose a flash type A/D (Analog-to-Digital) converter. This circuit uses a neuron CMOS inverter as a judgement component of the voltage level. It is smaller than traditional analog comparators in the power consumption and the layout area. Therefore, the power consumption and the layout area of this circuit can be reduced further compared with the conventional A/D converter using the analog comparator. Furthermore, we could confirm that the proposed circuit has a characteristic of high-speed operation.

A Dividing Ratio Changeable Digital PLL Using VCO as Base Clock Source

In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) using the VCO as the base clock source is proposed. In this circuit, the ratio of output jitter is not greatly influenced for the input signal. Also, the lock-in range can be widely compared with the conventional method.

A Dividing Ratio Changeable Digital PLL with Low Output Phase Noise

In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) which is difficult to receive the effect of the input phase noise is proposed. This circuit can realize the characteristic of a wide lock-in range and a fast pull-in.

All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter

This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.