Mohamed A. Abd El Ghany

High throughput architecture for high performance NoC

High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

Real-time efficient FPGA implementation of aes algorithm

An efficient optimized area and speed FPGA implementation for the Advanced Encryption Standard is proposed in this paper. The iterative looping method is adopted with multistage sub-pipelining architecture to achieve a 1.33 Gbps throughput for the AES-128 bit Encryption process. The proposed design operates at 425 MHz with 303 CLB slices on a Xilinx Virtex-5 XC5VLX50 FPGA Device. For real-time hardware evaluation, an end-user Java based application is developed. The software application is linked to the hardware design through the Xilinx MicroBlaze soft processor core.

A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations

3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D should be justified with improvements in performance, power or latency. To solve this problem, this paper presents a new simulation framework for 3D NoCs. We established a new Generic Scalable Pseudo Application (GSPA), where user can generate their own scalable pseudo applications. We have also integrated the state-of-the-art benchmarks to evaluate the 3D NoC system. In the framework, the 3D NoC with different vertical channel densities (VD) (i.e. number of Through-Silicon-Vias (TSVs)) can be generated according to the preference of users. After the simulation, the power consumption and system performance are evaluated. We have compared 2D NoC architecture with 3D NoC architecture with different VDs. The experimental results show that 3D architectures have significant advantage (Avg. 51%, 44%, 35% for 100%, 50%, 25% VD, respectively) in the aspect of interconnect power delay product in comparison to 2D mesh architecture. The 25% VD architecture is the best choice with 17% advantage over full connection (100% VD) 3D NoC architecture in the aspect of Figure of Merit which takes area and TSV connection yield into account among all the experiments for the given constrains.

High throughput architecture for CLICHÉ Network on Chip

High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

High throughput architecture for the Advanced Encryption Standard Algorithm

A high throughput architecture is proposed for an efficient implementation of the Advanced Encryption Standard (AES) Algorithm. The presented architecture is adapted for AES encryptor-only as well as integrated AES encryptor/decryptor designs. The SubBytes/InvSubBytes operations are implemented using composite field arithmetic in order to exploit the sub-pipelining advantage within the loop-unrolling methodology. The proposed architecture minimizes the critical path delay through the modification of the SubBytes/InvSubBytes as well as the KeyExpansion modules. Compared to previously reported AES encryptors and integrated AES encryptors/decryptors designs, the proposed architecture provides an efficiency improvement of 61% and 29% respectively.

Power efficient Networks on Chip

a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures. The technique reduces the power consumption of the network by up to 41%. When the power consumption of the whole network including the interswich links and repeaters is taken into account, the overall power consumption is decreased by up to 33% at the maximum operating frequency of the switch. The BFT architecture consumes the minimum power as compared to other NoC architectures.

Survey on Real-Time Networks-on-Chip

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field.

Highly reliable and power efficient NOC interconnects

Network on chip (NOC) architecture interconnects consume significant amount of power, have a large propagation delay and are susceptible to error due to deep sub-micron (DSM) noise. Major challenge that NOC design expected to face is related to intrinsic reliability. By incorporating error control coding schemes along the NOC interconnects, NOC architectures are able to provide correct functionality in the presence of different transient noise source. In this paper we present a novel coding scheme that increase the reliability of the NOC where the area is reduced by 19% and the consumed power by NOC interconnects is decreased by 51%. Butterfly fat tree architecture consumes the minimum power as compared to other NOC architectures.

Power analysis for Asynchronous CLICHÉ Network-on-Chip

Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous CLICHÉ switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the (αdata equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the (αdata. The total metal resources required to implement Asynchronous design is decreased by 7%.

Power characteristics of Networks on Chip

Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.