Mohamed Akil

A methodology to implement real-time applications onto reconfigurable circuits

This paper presents an extension of the AAA rapid prototyping methodology for the optimized implementation of real-time applications onto reconfigurable circuits. This extension is based on an unified model of factorized data dependence graphs as well to specify the application algorihtm, as to deduce the possible implementations onto reconfigurable hardware. This is formalized in terms of graphs transformations. This seamless transformation flow has been implemented in a CAD software tool called SynDEx-IC.

Parallel Algorithm for Concurrent Computation of Connected Component Tree

The paper proposes a new parallel connected-component-tree construction algorithm based on line independent building and progressive merging of partial 1-D trees. Two parallelization strategies were developed: the parallelism maximization strategy, which balances the workload of the processes, and the communication minimization strategy, which minimizes communication among the processes. The new algorithm is able to process any pixel data type, thanks to not using a hierarchical queue. The algorithm needs only the input and output buffers and a small stack. A speedup of 3.57 compared to the sequential algorithm was obtained on Opteron 4-core shared memory ccNUMA architecture. Performance comparison with existing state of the art is also discussed.

Shot noise adaptive bilateral filter

The bilateral filter (BF) is an important image denoising local filter. It reduces noise in images while preserving edges by means of nonlinear combination of local pixel values. Its formulation and implementation are both simple. However, the BF is not parameter-free. The set of the bilateral filter parameters has an important influence on its behavior and performance. They have to be chosen considering the end application. In the case of noise removal, the parameters have to be adapted to the noise level, while the bilateral filter adapts itself to the image details content. In this paper we propose a method to estimate the best bilateral filter intensity parameter set in the case of shot noise removal, the dominant form of natural noise in digital imaging.

Low level image processing operators on FPGA: implementation examples and performance evaluation

This work deals with evaluation of hardware implementations of image processing algorithms for real time applications, using SRAM based field-programmable gate arrays. We discuss a generic architectural model adapted to this domain and to the technology characteristics. A method to evaluate the area costs and timing performances of architectures implemented on such a model is presented. A feasibility study of a pre-processing chain in an image-recognition system is presented.

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.

Efficient Poisson denoising for photography

In general, image sensor noise is dominated by Poisson statistics, even at high illumination level, yet most standard denoising procedures often assume a simpler additive Gaussian noise, which is in fact a poor approximation. Fortunately, Poisson noise can under some circumstances be simplified via variance stabilizing methods, such as the Anscombe transform, which is well known to statisticians, medical imaging specialists and astronomers. However, in order to use such a procedure effectively, the actual photon count needs to be known and not simply an illumination intensity, which is the main reason why such procedures are not frequently used in the image processing community. In this article, we propose to use Poisson distribution characteristics to estimate the photon count from relative illumination data, under simple hypotheses. This allows us to use variance-stabilizing methods on standard digital photographs. Thanks to this, the noise becomes close to additive Gaussian and standard filtering methods become significantly more effective. As an example we exhibit the level of improvement that can be achieved using the bilateral filter.

Special issue on parallel computing for real-time image processing

The performance requirements of image processing applications have continuously increased, especially when they are executed under real-time constraints. We have organized this special issue on parallel computing for real-time image processing to present the current state-of-the-art in the field of parallel programming and the future trends in real-time image and video processing as related to parallel computing or real-time implementation of embedded image processing applications on parallel architectures including multi-core platforms, GPUs and dedicated parallel architectures. Due to the overwhelming number and their wide scope of submissions received for this special issue and thus the difficulty associated with finding expert reviewers, we have decided to offer this special issue in two or possibly three parts to meet the planned appearance of this special issue. The papers that are currently under review will appear in a second or a third part of this special issue immediately after their reviews and re-reviews are concluded. We are very grateful to the reviewers who provided valuable comments and suggestions to improve the quality of the accepted papers. This first part of the special issue on parallel computing for real-time image processing presents articles addressing GPU/Multi-GPU programming and is dedicated to parallel architectures based on FPGA and/or CMOS VLSI technologies for real-time image processing applications. Six papers appear in this first part. Brief outlines of these papers are stated below: The first paper by Anis Rahman, Dominique Houzet, Denis Pellerin, Sophie Marat and Nathalie Guyader describes a parallel implementation of a spatio-temporal visual saliency model with multi-GPU reaching a real-time throughput. This article focuses on the algorithms of this model and details several parallel optimizations. The second paper by Fernanda Palhano, Guillermo Andrade-Barroso and Pierre Hellier presents a method for real-time denoising of ultrasound images discussing a modified version of the NL-means method that incorporates an ultrasound dedicated noise model. It addresses a GPU implementation of this algorithm. Results demonstrate that the proposed method is quite efficient in terms of denoising quality and real-time performance. The third paper by Harald Jordan, Walter van Dyck and Rene Smodic describes a new approach for a contourtracking algorithm targeting a low power smart camera for industrial inspection. This embedded system consists of the three major components: CMOS sensor, FPGA and microprocessor. The fourth paper by Mathieu Thevenin, Michel Paindavoine, Laurent Letellier, Renaud Schmit, and Barthelemy Heyrman describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than

Real-time implementation of morphological filters with polygonal structuring elements

1 mm and 500 mW in TSMC 65 nm technology). The fifth paper by Loic Sieler, Lionel Damez, Landrault Alexis and Jean-Pierre Derutin presents the parallelization and the embedding of a real-time image stabilization algorithm on SoPC platform. The overall hardware implementation method is based upon meeting algorithm M. Akil (&) L. Perroton Universite Paris-Est, LIGM, Equipe A3SI, ESIEE Paris Cite Descartes, BP 99, 93162 Noisy-le-Grand Cedex, France e-mail: akilm@esiee.fr

From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: a Seamless Flow of Graphs Transformations

In mathematical morphology, circular structuring elements (SE) are used whenever one needs angular isotropy. The circles—difficult to implement efficiently—are often approximated by convex, symmetric polygons that decompose under the Minkowski addition to 1-D inclined segments. In this paper, we show how to perform this decomposition efficiently, in stream with almost optimal latency to compute gray-scale erosion and dilation by flat regular polygons. We further increase its performance by introducing a spatial parallelism while maintaining sequential access to data. We implement these principles in a dedicated hardware block. Several of these blocks can be concatenated to efficiently compute sequential filters, or granulometries in one scan. With a configurable image size and programmable SE size, this architecture is usable in high-end, real-time industrial applications. We show on an example that it conforms to real-time requirements of the 100Hz 1080p FullHD TV standard, even for serial morphological filters using large hexagons or octagons.

Study and implementation of a real time 3*3 programmable convolver with reconfigurable technology

The control, signal and image processing applications are complex in terms of algorithms, hardware architectures and real-time/embedded constraints. System level CAD softwares are then useful to help the designer for prototyping and optimizing such applications. These tools are oftently based on design flow methodologies. This paper presents a seamless design flow which transforms a data dependence graph specifying the application into an implementation graph containing both data and control paths. The proposed approach follows a set of rules based on the RTL model and on mechanisms of synchronized data transfers in order to transform automatically the initial algorithmic graph into the implementation graph. This transformation flow is part of the extension of our AAA (Algorithm-Architecture Adequation) rapid prototyping methodology to support the optimized implementation of real-time applications on reconfigurable circuits. It has been implemented in SynDEx, a system level CAD software tool that supports AAA.