Mohamed Krid

Hardware implementation of pulse mode RBF neural network-based image denoising

In this paper, we propose a very compact implementation of a pulse mode radial basis activation function (RBF). The main idea is to make use of the powerful means of RBF neural networks in function approximation and implement a reconfigurable hardware, achieving different image processing tasks with on-chip learning. The proposed network is applied here as illustration in image denoising, which is a very important step in image processing. The efficiency of the proposed pulse mode RBF neural network in image denoising versus other conventional filtering techniques is demonstrated. Moreover, it has been shown that the best strategy, leading to better learning generalisation performances, is to apply in the learning steps all kinds of noise in a random way. In such a way, generalisation is better with respect to each kind of noise. The corresponding design was implemented on a Virtex II PRO FPGA platform and synthesis results are presented.

Neural network based edge detection with pulse mode operations and floating point format precision

This paper proposes a pulse mode neural network based edge detection system. Edge detection of an image reduces significantly the amount of data and filters out information that may be regarded as less irrelevant. Edge detection is efficient in medical imaging. Known by their significant compactness pulse mode neural networks are becoming an attractive solution for function approximation based on frequency modulation. Early pulse mode implementation suffers from some network constraints due to weight range limitations. To provide the best edge detection, the backpropagation algorithm is modified to have pulse mode operations for effective hardware implementation. Here, we undergo these limitations with a new pulse mode network architecture using floating point operations in the activation function. By using floating point number system for synapse weight value representation, any function can be approximated by the network. The proposed pulse mode MNN is used to detect the edges in images forming a heterogenous data base. It shows good learning capability. The corresponding design was implemented into a virtex II PRO XC2VP7 Xilinx FPGA.

FPGA implementation of programmable pulse mode neural network with on chip learning

This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplierless architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a Virtex II PRO XC2VP7 Xilinx FPGA

FPGA Implementation of Programmable Pulse Mode Neural Network with on Chip Learning for signature application

This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplierless architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a Virtex II PRO XC2VP7 Xilinx FPGA

Hardware implementation of Neural-Fuzzy Network based image denoising approximation

In this paper, we propose a new architecture of Neural-Fuzzy Network (NFN) devoted to function approximation tasks. NFN with on chip learning offers the possibility of reconfiguration and the generality of the solution since it can approximate any input-output function through parameters update. Back-propagation learning algorithm constitutes an appropriate method that can make an efficient approximation of NFN parameters. In this context, the main idea is to implement the proposed NFN based on the back-propagation algorithm using Field Programmable Gate Arrays (FPGA). However, the complexity of such system, presents a drawback for hardware implementation. Therefore, we make use of pulse mode since it can support this problem thanks to its higher density of integration. To verify the proposed design performance, we consider image denoising function approximation as illustration example. Experimental results reveal the performance and efficiency of the proposed NFN versus other conventional filtering techniques. Synthesis results on a FPGA platform are presented and discussed.

Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing

A key task in the hardware implementation of neural networks is the design of activation functions. We focus in this paper on hardware driven simple implementation of a bell-shaped function BSF avoiding complexity and reducing hardware resources with efficient on-chip learning. This implementation is done in pulse mode to take advantage of its valuable features, significantly reducing the hardware cost. The proposed design is flexible and scalable enabling several image processing potential tasks. A first application is devoted to image denoising where a comparison with some existing denoising techniques demonstrates the efficiency of the proposed approach. As a second application, we consider edge detection operation and good approximation features are accordingly obtained. The corresponding design is implemented on a Virtex-II-PRO FPGA platform. Synthesis results prove that the bell-shaped PMNN is not cumbersome, and provides higher performances versus other PMNN architectures in terms of computing speed and required hardware resources.

A self-constructing neuro-fuzzy classifier for breast cancer diagnosis using swarm intelligence

In this paper, a self-constructing neuro-fuzzy (SCNF) classifier optimized by swarm intelligence technique is proposed for breast cancer diagnosis. The first step in the design is the definition of the fuzzy network structure. Accordingly, a rule generation approach with self-constructing property is proposed. Based on similarity measures, the given input-output patterns are organized into clusters. Then, membership functions are generated roughly to form a fuzzy rule base. To achieve accurate learning, particle swarm optimization (PSO) algorithm is used to adjust consequent and antecedent parameters of the obtained rules. Accordingly, a weighted function is constructed to design the objective function of the PSO, which takes into account the specificity, the sensitivity and the total classification accuracy of the proposed SCNF classifier. The proposed SCNF classifier is evaluated on the widely used Wisconsin breast cancer dataset (WBCD) for breast cancer diagnosis. Experimental results confirm that the proposed model is able to detect breast cancer with a classification accuracy of more than 99%. A comparative study has been elaborated confirming the best performance of the proposed classifier.

FPGA implementation of a modified pulse mode FCM image segmentation algorithms

This paper present a novel architecture for image segmentation. The design is based on the fuzzy c-means algorithm based gaussian function in pulse mode for reducing the large storage requirement. The proposed algorithm is tested in mammogram image segmentation approximately with 0.92 of segmentation index. The pulse mode stochastic computing technique is implemented with a simple bloc avoiding the use of conventional multipliers for sake of compactness. The whole modified FCM is implemented on a Virtex II PRO FPGA platform and synthesis results are presented.

Implementation of Neuro-Fuzzy System based image edge detection

In this paper, we propose an implementation of a Neuro-Fuzzy System (NFS) with on chip learning for achieving different image processing tasks such as filtering, edge detection, etc. The complexity of this kind of implementation makes the pulse mode an important approach to achieve our goal thanks to its higher density of integration. As validation example, we propose here the edge detection process to be approximated by this system. The proposed system has proven a good approximation ability with a reduced neuron number and learning time cost. Moreover, the efficiency of our proposed system versus conventional edge detection operators is demonstrated. For different error criteria, our design shows the lowest values. The designed system is implemented on a field-programmable gate array (FPGA) platform. Synthesis results prove that the implemented NFS provides the best compromise between compactness, speed and accuracy compared to previous works from literature.

2D Parallel Architecture for Morphological Operators Supporting Multiple Shaped Structuring Elements

Abstract This paper presents a reconfigurable 2D parallel architecture designed to implement efficiently two fundamental gray scale morphological operations: dilation and erosion. The architecture is expected to be used as a hardware core integrated in real time application. Moreover, the proposed architecture allows processing data on high resolution images with reconfigurable size and arbitrary shape of structuring elements. The main advantage of the proposed architecture is its low latency, higher throughput and higher processing frame rate. Additionally, the architecture processes data on stream which avoids the need of any buffering at input level. The architecture is successfully implemented and prototyped on Virtex-5 field programmable gate array. Implementation results show that the architecture can achieve high frame rate: for example, for a 1024x768 image and 11x11 structuring element, we reach a frame rate of 341 Fps.