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Dive into the research topics where Mohammad Abdallah is active.

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Featured researches published by Mohammad Abdallah.


IEEE Transactions on Signal Processing | 1999

Implementation issues of the two-level residue number system with pairs of conjugate moduli

Alexander Skavantzos; Mohammad Abdallah

One of the most important considerations when designing residue number systems (RNSs) is the choice of the moduli set; this is due to the fact that the dynamic range of the system, its speed, as well as its hardware complexity, depend on both the forms as well as the number of moduli chosen; In this paper, a new class of multimoduli RNSs based on sets of forms {2/sup n(1)/-1, 2/sup n(1)/+1, 2/sup n2/-1, 2/sup n(2)/+1, /spl middot//spl middot//spl middot/, 2/sup n(L)/-1, 2/sup n(L)/+1} is presented. The moduli 2/sup n(i)/-1 and 2/sup n(i)/+1 are called conjugates of each other. The new RNSs that rely on pairs of conjugate moduli result in hardware-efficient two-level implementations for the weighted-to-RNS and RNS-to-weighted conversions, achieve very large dynamic ranges, and imply fast and efficient RNS processing. When compared with conventional systems of the same number of moduli and the same dynamic range, the proposed new systems offer the following benefits: (1) hardware savings of 25 to 40% for the weighted-to-RNS conversion and (2) a reduction of over 80% in the complexity of the final Chinese remainder theorem (CRT) involved in the RNS-to-weighted conversion. Thus, significant compromises between large dynamic ranges, fast internal processing, and low complexity are achieved by the new systems.


IEEE Transactions on Signal Processing | 1997

On the binary quadratic residue system with noncoprime moduli

Mohammad Abdallah; Alexander Skavantzos

The residue number system (RNS) appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. A development in residue arithmetic is the quadratic residue number system (QRNS), which can perform complex multiplications with only two integer multiplications instead of four. An RNS/QRNS is defined by a set of relatively prime integers, called the moduli set, where the choice of this set is one of the most important design considerations for RNS/QRNS systems. In order to maintain simple QRNS arithmetic, moduli sets with numbers of forms 2/sup n/+1 (n is even) have been considered. An efficient such set is the three-moduli set (2/sup 2k-2/+1.2/sup 2k/+1.2/sup 2k+2/+1) for odd k. However, if large dynamic ranges are desirable, QRNS systems with more than three relatively prime moduli must be considered. It is shown that if a QRNS set consists of more than four relatively prime moduli of forms 2/sup n/+1, the moduli selection process becomes inflexible and the arithmetic gets very unbalanced. The above problem can be solved if nonrelatively prime moduli are used. New multimoduli QRNS systems are presented that are based on nonrelatively prime moduli of forms 2/sup n/+1 (n even). The new systems allow flexible moduli selection process, very balanced arithmetic, and are appropriate for large dynamic ranges. For a given dynamic range, these new systems exhibit better speed performance than that of the three-moduli QRNS system.


international conference on electronics, circuits, and systems | 2009

Design of a balanced 8-modulus RNS

Alexander Skavantzos; Mohammad Abdallah; Thanos Stouraitis; Dimitrios Schinianakis

In this paper the design of a balanced 8-modulus RNS system is presented. This RNS is based on the modulus set A = {2<sup>n−5</sup> − 1, 2<sup>n−3</sup> − 1, 2<sup>n−3</sup> + 1, 2<sup>n−2</sup> + 1, 2<sup>n−1</sup> − 1, 2<sup>n−1</sup> + 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}; n = 2k, k = 4, 5, 6, …, which comprises non co-prime moduli. The system is balanced, in the sense that adjacent moduli are of similar word length and achieve fast internal processing and dynamic ranges larger than 32 bits. Its weighted-to-RNS converter is an efficient two-level converter. Its RNS-to-weighted converter is a three-level converter based on a combination of an efficient Chinese Remainder Theorem (CRT), the Mixed Radix Conversion (MRC) technique and an efficient implementation of a 2-channel CRT based on non co-prime moduli.


Journal of Circuits, Systems, and Computers | 2007

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

Alexander Skavantzos; Mohammad Abdallah; Thanos Stouraitis

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a ones complement multi-operand adder that adds operands of size only 80% of the size dictated by the systems dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod(2x - 1) hardware, which can be easily implemented as ones complement hardware.


Archive | 2001

Executing partial-width packed data instructions

Mohammad Abdallah; James S. Coke; Vladimir Pentkovski; Patrice Roussel; Shreekant S. Thakkar


Archive | 1998

Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry

Mohammad Abdallah; Vladimir Pentkovski


Archive | 2001

Method and apparatus for floating point operations and format conversion operations

Mohammad Abdallah; Prasad Modali


Archive | 1998

Method and apparatus for efficient vertical SIMD computations

Mohammad Abdallah; Thomas Huff; Gregory C. Parrish; Shreekant S. Thakkar


Archive | 2001

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

Mohammad Abdallah; Hsien-Cheng E Hsieh; Thomas Huff; Vladimir Pentkovski; Patrice Roussel; Shreekant S. Thakkar


Archive | 2000

Hardware predication for conditional instruction path branching

Mohammad Abdallah; Khalid Al-Dajani

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