Mohammad Gholami

A novel architecture for low voltage-low power DLL-based frequency multipliers

New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupying low area, low power, low voltage and low phase noise. Also good stability can be obtained in this design. This structure also can be used for generating big multiples of reference frequency. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13um CMOS Technology.

A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers

Lock time and convergence time are the most important challenges in delay-locked loops DLLs. In this paper we cover French very high frequency band with a novel all-digital fast-lock DLL-based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells, and fREF=16MHz, which can produce output frequency in range of 176-216MHz. Locking time is approximately 0.3µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright

Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers

In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phase-frequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells and f REF = 16 MHz which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.5 μs which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.

Low voltage and low power DLL-based frequency synthesizer for covering VHF frequency band

New architecture for a DLL based frequency synthesizer for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. It was shown that for the mentioned standard a mere 27 delay stages for VCDL is sufficient. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13um CMOS technology.

Analysis of frequency and amplitude in CMOS differential ring oscillators

In this paper, a new method for computing the amplitude and frequency of differential ring oscillators (ROs) is proposed. The analysis is performed in two separate parts. In the first of these, equations are derived with the assumption of a sinusoidal waveform of outputs, while in the other, the outputs are assumed to be exponential. It is shown that the derived equations for frequency and amplitude are sufficiently exact. In addition, conditions in which sinusoidal and exponential output occur are thoroughly discussed. In the instances in which the results did not satisfy the necessary conditions for sinusoidal output, the output is assumed to be exponential. Moreover, the related analytical equations are written, and the new expressions for frequency and amplitude of ROs are derived. Analytical results are confirmed by simulation results, using the Taiwan Semiconductor Manufacturing Company 0.18?m technology model. The simulation results indicate the high level of accuracy of the proposed model. A new analytical approach is proposed for differential ring oscillators.The exact equations on the amplitude and frequency is derived in the proposed method.It provides the condition which the oscillator passes from being linear to nonlinear.Analytical results confirm the simulation results in 0.5 to 10GHz frequencies.

Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources

There are four main sources of jitter in delay-locked loops (DLLs). In this paper, DLLs jitter due to uncertainties in these sources of jitter is calculated. Time domain equations of DLL are introduced, which are the key parameters to obtain a closed-form equation related to jitter of DLL in the presence of noisy phase-frequency detector, charge pump, delay cells, and reference clock. First, DLLs jitter at the output of each delay cells due to each sources of the jitter will be calculated. Then, the obtained equations are used to calculate the total jitter at the output of all stages. Finally, a DLL is designed in the 0.18-μm CMOS technology to validate the obtained equations.

Jitter of Delay-Locked Loops Due to PFD

In this paper, delay-locked loops (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL is designed in 0.18-μm CMOS technology to validate the obtained equations.

Using a memristor crossbar structure to implement a novel adaptive real-time fuzzy modeling algorithm

Abstract Fuzzy techniques can be used for accurate and high-speed modeling as well as for the control of complex systems, but various challenging problems are usually encountered during their actual implementation. For example, the variable parameters need to be optimized iteratively during the training phase, where this process is inspired by crisp domain algorithms. However, in recent years, memristor-based structures have emerged as another promising method for implementing neural network structures and fuzzy algorithms. In this study, we propose a novel adaptive and real-time fuzzy modeling algorithm, which employs the active learning method concept to mimic the functionality of the brains right hemisphere. The proposed method processes fuzzy numbers such that the system retains its sensitivity to individual training data points, which expands the knowledge tree to allow plasticity, as well as using a specific defuzzification technique that guarantees stability. Another advantage of our new processing engine is that the nature of processing within the fuzzy system is consistent with that observed in memristive devices. Thus, we demonstrate that the proposed fuzzy architecture can be implemented easily and efficiently using existing crossbar structures. We verified the effectiveness of the proposed algorithm in modeling and pattern recognition tasks based on computer simulations.

New method to synthesize the frequency bands with DLL-based frequency synthesizer

This paper presents a new architecture for a DLL based frequency synthesizer. Occupying low area, lower power consumption and phase noise are the advantages of this novel architecture. DLLs are first ordered systems, so good stability can be obtained in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. A case in point, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit is designed based on 0.13um CMOS Technology. Also power consumption trade-offs are introduced. It was shown that 27 delay cells are sufficient to cover the mentioned standard. Simulation results confirm the analytical predictions.

A low power 1-V 10-bit 40-MS/s pipeline ADC

A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC achieves 56.04dB signal-to-noise ratio (SNDR), 9.02 effective numbers of bits (ENOB) and INL/DNL of less than 1 LSB, while consuming only 3.9 mW from a 1-V power supply. The Figure-of-Merit (FOM) value is less than 0.19 pJ/Conversion.