Mohammad Ullah Habib

Characterization of Single-Photon Avalanche Diodes in a 0.5- Standard CMOS Process—Part 2: Equivalent Circuit Model and Geiger Mode Readout

This paper features a model that allows the design and simulation of perimeter-gated single-photon avalanche diodes (SPADs). The model enables both Geiger mode and DC mode simulations. The models key parameters were extracted from measured characteristics of a perimeter-gated SPAD fabricated in a 3-metal, 2-poly, single well CMOS process. This paper also features a survey of state-of-the-art SPAD models. Last, this paper describes the design and measured characteristics of a pixel that includes a perimeter-gated SPAD and a mixed-signal readout circuit.

Optimization of perimeter gated SPADs in a standard CMOS process

Perimeter gated single photon avalanche diodes (PGSPADs) in standard CMOS processes have increased breakdown voltages and improved dark count rates. These devices use a polysilicon gate to reduce the premature breakdown of the device. This work characterizes the variation in PGSPAD noise (dark count rate) and breakdown voltage as a function of applied gate voltages for varying device shape, size, and junction type. Eight different PGSPADs were designed and fabricated in standard 0.5μm 2 poly, 3 metal CMOS process. Our study showed the size of the device has negligible effect on the breakdown voltage of the device. The dark count rate for a circular shaped device is higher than a square shaped device but the effect of excess bias on the noise of the circular shaped device is less. Using a psub/n-well junction instead of an n-well/p+ junction increased the breakdown voltage. The effects of five factors: the size, the shape, the type of junction, the excess bias voltage and the gate voltage were investigated in this work.

Perimeter-Gated Single-Photon Avalanche Diodes: An Information Theoretic Assessment

The performance of perimeter-gated single-photon avalanche diodes (PGSPADs) is assessed using principles of information theory. PGSPADs have an additional polysilicon gate to mitigate the effects of premature edge breakdown. Performance metrics of the photon detection probability and the dark count rate are experimentally obtained as functions of gate bias voltage and excess bias voltage. Applying the binary asymmetric communication channel model to the device, the parameter space that maximizes the information rate of the PGSPAD is assessed from the model and experimental data.

A perimeter gated single photon avalanche diode based silicon photomultiplier as optical detector

A CMOS silicon photomultiplier based on perimeter gated single photon avalanche diode was designed for optical detection applications. The photomultiplier was fabricated in a standard 0.5 μm 2 poly, 3 metal CMOS process. The perimeter gated single silicon photomultiplier shows an increase in breakdown voltage with increasing gate voltage. The noise floor of the detector was characterized as a function of applied gate bias and excess bias voltages. The sensitivity of the detector to incident optical illumination was characterized. The sensitivity of the detector is ~ 0.08A per W/cm2.

A SPICE model for perimeter-gated single photon avalanche diode

In this work a comprehensive SPICE model is demonstrated for perimeter-gated single photon avalanche diodes (PGSPAD) fabricated in commercial 0.5 μm CMOS process. This model simulates the trigger of an avalanche event of PGSPAD due to photon absorption, along with the quenching behavior. It also simulates the I-V characteristic, where the breakdown voltage can be modulated with applied gate voltage. The modeling parameters are experimentally extracted from fabricated PGSPADs. This model simulates both the static and dynamic behaviors of the device. Simulated results are validated with experimental data to demonstrate the accuracy of the model.

A Tunable Dynamic Range Digital Single Photon Avalanche Diode

We characterize a digital, tunable dynamic range, single photon avalanche diode (SPAD) pixel fabricated in a standard 0.5 μm, 2-poly, 3-metal CMOS process. The principal sensor used in the pixel is based on the perimeter gated SPAD. The perimeter gate enhances device performance through prevention of premature breakdown, with the added advantage of a tunable dynamic range. Experimental measurements of the signal-to-noise ratio over the visible spectral range show the perimeter gate improves the dynamic range at a small expense of the sensitivity.

A low power integrated bowel sound measurement system

Bowel signal monitoring finds numerous applications in medical and pathological fields. A portable bowel sound monitoring system requires front end amplifiers, data converters, signal processors and power efficient operation. In this paper, a low power integrated bowel sound monitoring system has been proposed and implemented. The system consists of a tunable charge amplifier, a feature extraction block, a bowel sound detection unit and a bowel sound occurrence rate count block. The system is implemented in a standard 6 metal 1 poly 180nm CMOS process. The developed integrated system consumes 52μW of power from a 1V supply.

A low-power low-noise transimpedance amplifier for an integrated biosensing platform

In this paper, we design a low power, low noise transimpedance amplifier for ultra-low biosignal amplification. The proposed transimpedance amplifier is implemented in a standard 6 metal, 1 poly 0.18μm CMOS process. The amplifier is capable of producing 215MΩ transimpedance gain, 0.615MHz bandwidth; 910fA/√Hz input referred noise at 100Hz while consuming only 139μW DC power.

A 10.6μm × 10.6μm CMOS SPAD with integrated readout

Single photon avalanche diodes (SPAD) are sensitive optical sensing tools. Incoming photons trigger avalanche events resulting in large device currents. In this paper, we show experimental results for a 10.6 μm × 10.6 μm perimeter gated SPAD with integrated readout circuitry in 0.5 μm 2 poly, 3 metal standard CMOS process. The dark count rate demonstrates a functional relationship with the gate and the excess bias voltage. A compact readout topology is used which takes advantage of the Miller effect to reduce the readout area footprint, thus increasing the pixel fill factor.

Improved signal to noise ratio across the spectral range for CMOS silicon photomultipliers

We report on a CMOS silicon photomultiplier (SiPM) with 9×18 microcells fabricated in a 0.5μm 2-poly 3-metal standard CMOS process. The microcells use perimeter gated single photon avalanche diodes (PGSPADs) to vary the SiPM device signal to noise ratio by modulating the electric field around the junction of the PGSPADs. Experimental measurements show that the SNR can be improved over a range of 1 to 1000 tuning the perimeter gate voltage and excess bias voltage. The technique allows for SNR optimization and tuning dependent on the application.