Mohammad Hashem Haghbayan

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach

Power management of NoC-based many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.

Dark silicon aware runtime mapping for many-core systems: A patterning approach

Limitation on power budget in many-core systems leaves a fraction of on-chip resources inactive, referred to as dark silicon. In such systems, an efficient run-time application mapping approach can considerably enhance resource utilization and mitigate the dark silicon phenomenon. In this paper, we propose a dark silicon aware runtime application mapping approach that patterns active cores alongside the inactive cores in order to evenly distribute power density across the chip. This approach leverages dark silicon to balance the temperature of active cores to provide higher power budget and better resource utilization, within a safe peak operating temperature. In contrast with exhaustive search based mapping approach, our agile heuristic approach has a negligible runtime overhead. Our patterning strategy yields a surplus power budget of up to 17% along with an improved throughput of up to 21% in comparison with other state-of-the-art run-time mapping strategies, while the surplus budget is as high as 40% compared to worst case scenarios.

MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip

Increasing dynamic workloads running on NoC-based many-core systems necessitates efficient runtime mapping strategies. With an unpredictable nature of application profiles, selecting a rational region to map an incoming application is an NP-hard problem in view of minimizing congestion and maximizing performance. In this paper, we propose a proactive region selection strategy which prioritizes nodes that offer lower congestion and dispersion. Our proposed strategy, MapPro, quantitatively represents the propagated impact of spatial availability and dispersion on the network with every new mapped application. This allows us to identify a suitable region to accommodate an incoming application that results in minimal congestion and dispersion. We cluster the network into squares of different radii to suit applications of different sizes and proactively select a suitable square for a new application, eliminating the overhead caused with typical reactive mapping approaches. We evaluated our proposed strategy over different traffic patterns and observed gains of up to 41% in energy efficiency, 28% in congestion and 21% dispersion when compared to the state-of-the-art region selection methods.

A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era

In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST

This paper presents a novel approach for selecting optimal pseudo random and deterministic test patterns and minimizing test time for multi-clock domain SoCs based on a hybrid BIST architecture for each core. For test scheduling, a concurrent method considering peak power upper bound is used. A test scheduling graph is presented for modeling concurrent hybrid BIST test scheduling. Furthermore, a heuristic is proposed for selecting cores to be tested concurrently and the order of applying sequence of test patterns to each core. Experimental results show that the proposed heuristics for both selecting groups of cores to be tested concurrently during the SoC test process, and determining the amount of deterministic and pseudo random test patterns for each core, give us an optimized method for multi clock domain SoC testing compared with the existing methods.

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

In this paper we are revisiting the issue of sequential circuit test generation, and use a selective random pattern test generation method implemented in an HDL environment. The method uses a statistical expectation graph and states of the sequential circuit for selecting the appropriate test vectors to achieve better fault coverage and a more compact test set. To further reduce the size of the generated test set, a static compaction method, which is also implemented in an HDL environment, is used after the test generation process. The experimental results show that selecting good test patterns among random test patterns, not only can be implemented dynamically in an HDL design environment, but also results in a better fault coverage and shorter test pattern length in comparison with some traditional deterministic methods. In addition, it will be shown that static test set compaction methods can considerably reduce the test length of test patterns for sequential designs obtained by our proposed method.

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism

Arithmetic circuits require a verification process to prove that the gate level circuit is functionally equivalent to a high level specification or not. Furthermore, if two models are not equivalent, we need to automatically localize bugs and correct them with minimum user intervention. This paper presents a formal technique to verify and debug arithmetic systems including dividers. The proposed technique is based on a reverse-engineering mechanism of obtaining a high level model of the gate level implementation and also presenting the specification at a lower level of abstraction which makes the equivalence checking between two models possible. During this process, if two high level models are not equivalent, possible bugs can be localized and then corrected automatically if possible. We have applied our technique to a wide range of arithmetic circuits including dividers, multipliers and their combinations. Preliminary experimental results show robustness of the proposed technique in comparison with other contemporary methods in terms of the run time. In average, two orders of magnitude average speedup is obtained.

Online testing of many-core systems in the Dark Silicon era

As the dark silicon era is about to embrace, it is not anymore possible to attain commensurate performance benefits by increasing the number of transistors due to thermal design power. Dark Silicon issue stresses that a fraction of silicon chip being able to switch in full frequency is dropping and designers will soon face the growing underutilization inherent in future technologies. On the other hand, by reducing the transistor size, susceptibility to internal defects drastically increases and large ranges of defects such as aging or transient faults will be shown up more frequently. In this paper, we propose an online test scheduling algorithm using software based self-test for dark silicon era to test dark cores while considering thermal design power of the system. As the dark area of the system is dynamic and reshapes at a runtime, the tested cores can be used by other applications in the near future. Empirical results show the effectiveness of the proposed algorithm in terms of applicability and fault coverage with a negligible negative impact on the system throughput.

Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era

Power management of networked many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates considering network characteristics at runtime to achieve better performance while honoring the peak power upper bound. On the other hand, power management has a direct effect on chip temperature, which is the main driver of the aging effects. Therefore, alongside performance fulfillment, the controlling mechanism must also consider the current cores’ reliability in its actuator manipulation to enhance the overall system lifetime in the long term. In this paper, we propose a multiobjective dynamic power management technique that uses current power consumption and other network characteristics including the reliability of the cores as the feedback while utilizing fine-grained voltage and frequency scaling and per-core power gating as the actuators. In addition, disturbance rejecter and reliability balancer are designed to help the controller to better smooth power consumption in the short term and reliability in the long term, respectively. Simulations of dynamic workloads and mixed criticality application profiles show that our method not only is effective in honoring the power budget while considerably boosting the system throughput, but also increases the overall system lifetime by minimizing aging effects by means of power consumption balancing.

Online Test Macro Scheduling and Assignment in MPSoC Design

Due to unreliability of the cores in embedded systems in deep sub-micron technologies, a method for testing cores in the field is needed. In this paper an online method for testing cores of embedded designs is presented. The proposed task scheduling method runs the test routine ASAP periodically considering the real time constraints. A software test routine based on a proposed method will be generated and a task scheduling process including the test task (for each core) and other existing applications of the embedded system will be presented. A software based checksum is issued for online test result analysis that shortens the memory usage of the test process. Experimental results show that this method improves the test application time (TAT) and fault coverage (in proportion to TAT) as compared with the existing methods.