Mohammad Hekmat

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays

The continuous increase in the resolution, color depth and refresh rate of TVs has driven the video data rate of the display panel interface from the timing controller to the pixel drivers in a typical 4K (UHD) TV to 36Gb/s. For the next generation 8K (Quad-UHD) TV, this number is expected to exceed 140Gb/s. The ever-increasing screen sizes pose an additional challenge by introducing high channel losses in the data lanes, requiring advanced equalization techniques such as decision feedback equalization (DFE) in the receiver, which hitherto has not been used in a display panel interface. At the same time, the requirement to integrate the receiver into the high-voltage pixel driver IC limits the technology of choice to 0.18μm CMOS. To achieve the required high-speed performance while accommodating process speed limitations, significant architectural and circuit improvements over the existing state-of-the-art are needed. This paper presents a complete 4-lane transceiver design, with each lane capable of operating up to 6Gb/s over a 24dB-loss channel while supporting both forwarded and embedded clocking modes. The receiver (Rx) in 0.18μm CMOS features a 5-tap quarter-rate predictive DFE (prDFE) architecture with the first tap implemented through body biasing, and taps 2-5 optimized to meet the timing requirement of the DFE feedback loop. The transmitter (Tx) in 65nm CMOS features a 3-tap FFE equalizer and a dual-VCO LC PLL with automatic resonance frequency tuning to cover a wide operating range.

Session 11 — Wireline building blocks

This session offers potpourri of advanced subjects for the design of wireline systems. The first paper is a clock multiplier that provides excellent jitter performance (−247db FOM) at 10GHz in a 65nm process using injection locking. The traditional problems of free running frequency drift are addressed with a novel continuous tracking loop.