Mohammad M. Mansour

A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes

This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.

Energy minimization feedback loop for ripple carry adders

We present a technique and related system implementation for minimizing energy consumption in ripple carry adder blocks, and we show simulation results for the various system blocks. The method includes a tracking loop which measures the energy consumed by the load and controls, through a DC-DC converter, the supply voltage of the load. The energy consumption of the adder is calculated for a range of inputs in order to verify the efficiency of the tracking loop. Results corresponding to an 8-bit ripple carry adder show that energy savings of the order of 50%-100% are expected to be obtained when all the blocks of the circuit are running together. The system is simulated using HSPICE and Verilog-A.

1.5 GHz robust SRAM array employing dynamic power management scheme

A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a total area of 0.370 mm2. A dynamic supply voltage management scheme is used to reduce the leakage power in the standby mode. The 64 kbits sub-array operates at 1.54 GHz for 1.0V supply voltage. Monte carlo simulation results show that the macro has a 6% failure probability under Vt process variations.