Mohammad Mojtaba Ebrahimi

Delta-sigma-based transmitters: Advantages and disadvantages

Power efficiency is one of the most important parameters in designing communication systems, especially battery operated mobile terminals. In a typical transceiver, most of the power is dissipated in the power amplifier (PA) and consequently, it is very important to obtain the maximum efficiency from the PA. A PA operating in Class AB or B is at its maximum efficiency when it is driven by its maximum allowable input power [1]. In practice, the input signal of the PA usually has a varying envelope, and to avoid distortion the PA should not be driven to more than its maximum input saturating power. Unfortunately, this peak power of the input signal happens at very short periods, and most of the time the signal power is around its average power, which is much smaller than its peak power, meaning that, often, the PA works at much lower efficiencies than its maximum efficiency. The power difference is defined as the peak to average power ratio (PAPR) of the signal. For example, for a signal with 12 dB PAPR, a Class B PA would be driven with 12 dB power back-off from its peak input power, and at this power back-off, the efficiency of the PA will degrade from 78.5% to around 20% [1]. Unfortunately, by moving to high throughput modulation schemes, for example, quadrature amplitude modulations (QAMs) such as 16-QAM and 64-QAM mean that more envelope variation is needed to encode the information, and, consequently, lower efficiency is achieved.

Time-Interleaved Delta-Sigma Modulator for Wideband Digital GHz Transmitters Design and SDR Applications

This paper presents a development of a wideband delta- sigma modulator for fully digital GHz transmitters. The fully digital RF transmitter is developed as a promising solution for software deflned radio (SDR) terminals and applications. The fully digital transmitter consists of a delta-sigma modulator, a high- speed multiplexer and a switching-mode power amplifler. The speed limitation of delta-sigma modulator is the main limitation to increase the signal bandwidth in fully digital transmitters. In this paper, the bandwidth of the fully digital transmitter is increased 8 times using parallel processing time-interleaved architecture, while maintaining the same signal quality. This architecture was implemented on FPGA and tested for difierent standards (WiMAX and LTE) with a signal bandwidth up to 8MHz. The concept was assessed in terms of SNDR by using a difierential logic analyzer at the output of FPGA, and the SNDR was found to be around 60dB.

Inverse Class F Power Amplifier for WiMAX Applications with 74% Efficiency at 2.45 GHz

This work proposes the steps to design a high efficiency inverse class F power amplifier (PA). In the first step, the optimal termination conditions for the inverse class F are extracted through load-pull measurement. Afterward, low loss and precisely tunable output matching network was chosen in order to obtain high efficiency of the PA. The fabrication of an inverse class F power amplifier for WiMAX applications at a carrier frequency equal to 2.45 GHz following the described design procedure is carried out and the obtained results demonstrate a measured power added efficiency equal to 71.5% and drain efficiency equal to 74%.

Reducing Quantization Noise to Boost Efficiency and Signal Bandwidth in Delta–Sigma-Based Transmitters

This paper introduces two new techniques to enhance both efficiency and signal bandwidth in delta-sigma-based transmitters. At first step, a technique called quantization noise reduction (QNR), is introduced to enhance the coding efficiency. By filtering out part of the quantization noise in the whole band of the signal, while the signal envelope is maintained almost constant, the coding efficiency is improved without imposing any additional nonlinearity or distortion to the system. By utilizing this technique for an orthogonal frequency division multiplexing (OFDM) signal with 1.25-MHz bandwidth and 80 times oversampling, with 8.1-dB peak-to-average power ratio (PAPR), the coding efficiency is improved from 8.8% to 14.5% while the signal-to-noise distortion ratio (SNDR) of the system remains 43 dB. In the next step by using a controlled filtering on in-band quantization noise along with QNR technique, the bandwidth of the signal and efficiency are increased simultaneously without losing as much linearity. The second technique is called quantization noise reduction with in-band filtering or (QNRIF). QNRIF is applied on an OFDM signal with 1.25-MHz bandwidth, with the same PAPR and only 16 times oversampling. The result for the coding efficiency is improved from 7.7% to 18.7% with 41-dB SNDR.

Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters

This paper proposes a complete transmitter prototype for wireless applications using envelope tracked pulsed gate modulated power amplifier (PA). The proposed transmitter architecture is developed using two high power 10 W gate modulated PAs combined in a fashion to operate as a switched voltage source for the range of duty cycles of pulses driving the gates of power amplifiers. These PAs are designed and implemented using packaged GaN HEMT transistors from CREE to operate at the carrier frequency of 2.35 GHz. For a 5 MHz bandwidth WiMAX 802.16e down-link signal with the PAPR of 7.9 dB and the oversampling ratio of 100, the average drain efficiency of 46.2% is achieved at the average output power of 35.8 dBm. Using a 5 MHz bandwidth LTE down-link signal with 11 dB PAPR and centered at 2.35 GHz, the power amplifier delivers the average output power of 33.2 dBm with the average drain efficiency of 46%. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -36.85 dBc at 10 MHz offset from the center frequency of 2.35 GHz.

Improving Coding Efficiency by compromising linearity in delta-sigma based transmitters

In this paper the Coding Efficiency in multi-bit delta-sigma based transmitters has been improved significantly by only adjusting the quantizers threshold values. To achieve this, the transmitters linearity should be compromised. Usually the space between thresholds in a quantizer of a multi-bit delta-sigma modulator is uniform which not the optimum choice is for Coding Efficiency. For an LTE signal with 3.84 MHz bandwidth and 16 times oversampling, the Coding Efficiency improves from 11.3% to 23.9% and from 31.2% to 48.7% by only changing the quantizers threshold values in a 3-level and a 5-level multi-bit delta-sigma modulators respectively. However, their Signal to Noise and Distortion Ratios degrade from 45.1 dB to 35.0 dB and from 51 dB to 42 dB respectively.

GaN polar transmitter design for base-station applications

In this paper a comparative study of 10 watt GaN polar transmitters for base-station application is carried out. Two main topologies are compared and studied. In the first topology, the drain of the transistor is modulated with the pulse format of the signals envelope, and in the modified topology, the gate of the transistor is modulated with the pulse format of the signals envelope. The transmitters are compared for two main parameters, the power efficiency and the signal quality. After a brief description of both topologies, their advantages and disadvantages are described, especially in terms of efficiency and signal quality. A LTE signal with the bandwidth of 1.4 MHz, the PAPR of 7.2 dB and the sampling rate of 64 is used for comparison purposes. Using the LTE signal, the polar architecture with modulated drain bias is able to achieve an SNDR of 42 dBc and the drain efficiency of 44%, while an SNDR of 35 dBc and the drain efficiency of 53% are obtained for the modified polar transmitter with the gate bias modulation.

Minimizing matching network loss in output harmonic matched power amplifiers using harmonic load-pull measurement

This paper proposes a harmonic matching network with minimum loss based on precise harmonic load pull measurement to enhance the efficiency and gain for harmonic matched power amplifiers. In this method, the number of stubs for harmonic matching network was reduced in order to minimize the loss and increase the efficiency. A power amplifier with a GaN transistor at 2.45 GHz frequency was designed to test and validate the approach. The fabricated power amplifier showed an improvement of around 0.2 dB in the loss of the output matching network, which corresponds to an improvement of more than 3% in the power amplifier efficiency compared to a conventional harmonic matching network. This new matching topology allowed reaching 72.9% drain efficiency and 14.46 dB gain.

Feedback-based digital predistorter for multi-bit delta-sigma transmitter

This paper proposes a feedback-based digital predistortion technique for multi-bit delta-sigma transmitters. This topology is based on a 3-bit delta-sigma modulator with a look-up table model of the power amplifier in the feedback loop. This feedback-based digital predistortion technique avoids the reverse modeling step found in conventional digital predistortion. Since the feedback loop is fully digitally implemented, the proposed architecture is not limited in terms of bandwidth, as is the case for conventional Cartesian feedback. System-level simulations and measurements have been carried out for evaluation of the performance of the proposed topology. It has been tested using a WiMAX signal, and the signal-to-noise-and-distortion ratio of the signal was improved by more than 20 dB and 10 dB in the simulation and measurement scenarios, respectively.

Trading-off stability for efficiency in designing switching-mode GaN PAs for WiMAX applications

This paper presents a 10W, 2.4 GHz switching-mode power with a GaN HEMT transistor for WiMAX applications. By trading the stability for the efficiency, the overall power efficiency of the designed PA can be increased. It is shown in this paper that the parasitic effect introduced by the stability circuit affects the waveform shaping at large-signal drive level in switching mode PAs and consequently degrades its maximum peak efficiency. Hence, by using a potentially instable design, the efficiency and gain performance of a given transistor can be increased compared to an unconditionally stable design. To validate this approach an inverse class F PA was manufactured and tested. The power added efficiency and gain performance increased by 3.5% and 0.25 dB to reach 72% and 14.5 dB, respectively, when using a potentially instable design.