Mohammadreza Yazdani

On construction of rate-compatible low-density Parity-check codes

In this letter, we present a framework for constructing rate-compatible low-density parity-check (LDPC) codes. The codes are linear-time encodable and are constructed from a mother code using puncturing and extending. Application of the proposed construction to a type-II hybrid automatic repeat request (ARQ) scheme with information block length k=1024 and code rates 8/19 to 8/10, using an optimized irregular mother code of rate 8/13, results in a throughput which is only about 0.7 dB away from Shannon limit. This outperforms existing similar schemes based on turbo codes and LDPC codes by up to 0.5 dB.

On minimizing the sum ofensor movements for barrier coverage of a line segment

A set of sensors establishes barrier coverage of a given line segment if every point of the segment is within the sensing range of a sensor. Given a line segment I, n mobile sensors in arbitrary initial positions on the line (not necessarily inside I) and the sensing ranges of the sensors, we are interested in finding final positions of sensors which establish a barrier coverage of I so that the sum of the distances traveled by all sensors from initial to final positions is minimized. It is shown that the problem is NP complete even to approximate up to constant factor when the sensors may have different sensing ranges. When the sensors have an identical sensing range we give several efficient algorithms to calculate the final destinations so that the sensors either establish a barrier coverage or maximize the coverage of the segment if complete coverage is not feasible while at the same time the sum of the distances traveled by all sensors is minimized. Some open problems are also mentioned.

On construction of rate-compatible low-density parity-check codes

This paper deals with the problem of devising an efficient framework for constructing rate-compatible low-density parity-check (RC-LDPC) codes. We present a deterministic framework for constructing a family of linear-time encodable RC-LDPC codes from a mother code using puncturing and extending. Application of the proposed construction to a type-II hybrid ARQ scheme with information block length k=1024 and code rates 8/19 to 8/10, using an optimized irregular mother code of rate 8/13, results in a throughput which is only about 0.7dB away from Shannon limit. This outperforms existing similar schemes based on turbo codes and LDPC codes by up to 0.5dB.

Irregular rate-compatible LDPC codes for capacity-approaching hybrid-ARQ schemes

In this paper, we describe the construction method of a family of irregular rate-compatible low-density parity-check (LDPC) codes by a combination of puncturing and extending techniques. In particular, we introduce a suitable structure for the extended parity-check matrices which preserves the structure of LDPC codes during extensions. Based on this construction, a family of efficient rate-compatible linear-time encodable codes are generated from an optimized irregular mother code of rate 8/13 and information block length k=1024. The rates of the codes vary from 8/10 to 8/19 and employing them in a type-II hybrid ARQ scheme results in a throughput which is only 0.7 dB away from the Shannon limit. This improves over the existing schemes, based on turbo codes and LDPC codes, by up to 0.5 dB.

Two Level State Machine Architecture for Content Inspection Engines

Content inspection technology is promising to address the growing demands of network security and contentaware networking. The component of a network device responsible for content inspection is called Content Inspection Engine (CIE). In content inspection processing, both headers and payload of packets are parsed to determine their content and classify them based on administrative policies. Due to the inclusion of complex payload processing in content inspection, a large amount of processing is required for each data packet, making content inspection a primary bottleneck in high performance routers that support gigabit link capacities. Therefore, there is a need for solutions that can inspect packets quickly with reasonable amount of storage requirements. We describe an architecture based on high performance state machines which provides an efficient solution to this problem by processing multiple characters per state transition. In this architecture the CIE is implemented on a Two-Level State Machine (TLSM). The TLSM implementation exploits the dependencies of policy rules to compress the policy and reduce memory requirements. Using TCAM units in the TLSM for performing fast multiple-character matching operations, makes a wire-speed content inspection possible. We also propose to use a new criterion called worstcase throughput as an appropriate metric for speed evaluation of CIEs. It is shown that this criterion can be efficiently calculated by applying existing algorithms for the Minimum Weight to Time Ratio problem, to a graph-based model of the functionality of CIEs.

A Criterion for Speed Evaluation of Content Inspection Engines

The growing needs of network security and contentaware networking increasingly introduce content processing into the network devices as opposed to the network endpoints. The component of a network device responsible for content inspection is called Content Inspection Engine (CIE). As other components of a network device, the CIE needs to operate at wire-speed, posing a need to look for an appropriate speed-evaluation criterion for CIEs. For processes with constant or at most well-bounded per-packet analyzes (e.g., routing, multi-field packet classification), and processes with flat per-byte processing time (e.g., checksum calculation, encryption/decryption), operation speed is traditionally evaluated in terms of the number of packets or bits processed per second. Such metrics cannot be used for processes in which the processing time of a packet varies widely, depending on its content. We propose to define worst-case throughput as a criterion for evaluating the wire-speed processing capabilities of CIEs. We argue that one may build simple model of a CIE, whether hardware or software based, in the form of a directed graph with edges annotated by the length and processing time of the segments of input data. It is then possible to transform the problem of finding the worst-case throughput of a CIE to the minimum cost to time ratio problem, for which many efficient algorithms exist.

Computing the throughput of Concatenation State Machines

Concatenation State Machine (CSM) is a labeled directed And-Or graph representing a deterministic push-down transducer. In the high-performance version of CSM, labels associated to edges are words (rather than letters) over the input alphabet. The throughput of a path p is defined as the sum of the lengths of the labels of the path, divided by the number of edges of p. The throughput of a CSM M is defined as the infimum of the throughput of all accepting paths of M. In this paper we give an O(nmlog(max-min@e)) algorithm, computing an @e-approximation of the throughput of a CSM M, where n is the number of nodes, m is the number of edges, and max (min) is the maximum (respectively, minimum) of the lengths of the edge labels of M. While we have been interested in a particular case of an And-Or graph representing a transducer, we have actually solved the following problem: if a real weight function is defined on the edges of an And-Or graph G, we compute an @e-approximation of the infimum of the complete hyper-path mean weights of G. This problem, if restricted to digraphs, is strongly connected to the problem of finding the minimum cycle mean.