Mohammed F. Tolba

FPGA realization of Caputo and Grünwald-Letnikov operators

This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators. The Grünwald-Letnikov and Caputo definitions are realized for different fractional orders. The realization is based on non-uniform segmentation algorithm with a variable lookup table. A generic implementation for Grünwald-Letnikov is proposed and a 32 bit Fixed Point Booth multiplier radix-4 is used for Caputo implementation. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance and other techniques for area and delay minimization have been employed. A comparison between the two presented architectures is introduced. The proposed designs have been simulated using Xilinx ISE and realized on FPGA Xilinx virtex-5 XC5VLX50T. The total area of 2515 look up tables is achieved for Caputo implementation, and maximum frequency of 54.11 MHz and 1498 slices are achieved for Grünwald-Letnikov architecture.

FPGA realization of ALU for mobile GPU

Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up the multiplier operation. The proposed ALU is designed using Verilog and verified using Xilinx Virtex-5 XC5VLX30 FPGA.

Proceedings of the International Conference on Advanced Intelligent Systems and Informatics 2016

This book gathers the proceedings of the 2nd International Conference on Advanced Intelligent Systems and Informatics (AISI2016), which took place in Cairo, Egypt during October 2426, 2016. This international interdisciplinary conference, which highlighted essential research and developments in the field of informatics and intelligent systems, was organized by the Scientific Research Group in Egypt (SRGE) and sponsored by the IEEE Computational Intelligence Society (Egypt chapter) and the IEEE Robotics and Automation Society (Egypt Chapter). The books content is divided into four main sections: Intelligent Language Processing, Intelligent Systems, Intelligent Robotics Systems, and Informatics.