Mohammed Sayeed

Multiple-bus multiprocessor under unbalanced traffic

Performance evaluation of multiple-bus multiprocessor systems is usually carried out under the assumption of uniform memory reference model. Hot spots arising in multiprocessor systems due to the use of shared variables, synchronization primitives, etc. give rise to non-uniform memory reference pattern. The objective of this paper is to study the performance of multiple bus multiprocessor system in the presence of hot spots. Analytical expressions for the average memory bandwidth and probability of acceptance of prioritized processors have been derived. Two new phenomenon, coined as bumping and knee effect, have been observed in the acceptance probabilities of the processors. The results are validated by simulation results.

Performance of multiple-bus multiprocessor under non-uniform memory reference

Performance evaluation of multiple-bus multiprocessor systems is usually carried out under the assumption of uniform memory reference model. The objective of this paper is to study the performance of multiple bus multiprocessor system in the presence of hot spots. Analytical expressions for the average memory bandwidth and probability of acceptance of prioritized processors have been derived. Two new phenomenon, coined as bumping and knee effect, have been observed in the acceptance probabilities of the processors. The results are validated by simulation results.<<ETX>>

Performance of Multiple-Bus Multiprocessor Under Non-Uniform Memory Reference Model

Performance evaluation of multiple-bus multiprocessor systems is usually carried out under the assumption of uniform memory reference model. Hot spots arising in multiprocessor systems due to the use of shared variables, synchronization primitives etc., give rise to non-uniform memory reference patterns. The objective of this paper is to study the performance of multiple bus multiprocessor system in the presence of hot spots. Analytic expressions for the average memory bandwidth and probability of acceptance of prioritized processors have been derived. The results are validated by simulation results.

Effect of non-uniform memory request on the performance of buffered multiprocessor systems

Abstract Performance analysis of multiple-bus systems is usually carried out under the assumption of a uniform memory request model. Hot spots arising in multiprocessor systems give rise to non-uniform memory requests. It is known that a hot spot memory request pattern results in a significant degradation in the performance of a buffered multistage interconnection network. The aim of this research is to study the effect of hot spots on the performance of buffered multiple-bus systems, and to compare the performance of buffered and unbuffered systems. Analytical models based on Markov chains have been developed to determine the bandwidth of buffered multiple-bus systems in the presence of a hot spot memory request pattern. The models assume that unsuccessful memory requests are queued in the buffers at the memory modules. Furthermore, processors with outstanding requests are not allowed to generate new requests. The model allows a fast and inexpensive method to evaluate the performance of a buffered multiple-bus system in the presence of a hot spot memory request pattern.

Modeling of Buffered Multiple Bus Multiprocessor Systems in a Non-Uniform Traffic Environment

Performance modeling of multiple-bus systems is usually carried out under the assumption of uniform memory reference model. Hot spots arising in multiprocessor systems give rise to non-uniform memory references. I t is known that a hot spot memory reference pattern results i n a significant degradation in the performance of Q buffered multistage interconnection network. The aim of this research is t o study the effect of hot spots on the performance of buffered multiple-bus systems. Analytical models based on Markov chains have been developed to determine the bandwidth of buffered multiple-bus systems in a hot spot memory reference pattern. The models assume that unsuccessful memory requests are queued an the buffers at the memory modules. Furthermore, processors with outstanding requests are not allowed to generate new requests. The model allows a fast and inexpensive method of performance evaluation of a multiple bus system in the case of a hot spot memory reference pattern.