Mohit Arora

A "Stitch" in Time: Accurate Timekeeping with On-Chip Compensation

Applications like Energy Meters that rely on real time data require accurate time under all environmental conditions. Typically, these applications rely on Real Time Clock (RTC) for all real time operations but there are many factors like crystal aging, incorrect loading and temperature variations that tend to change the frequency of the clock used for RTC resulting in inaccurate time. Hence there is an unavoidable need to have compensation technique inside the RTC to counter balance this error in clock frequency of crystal. This paper describes a digital hardware compensation technique which compensates by adding or removing pulses in a particular timing window thus maintaining accurate clock. Technique described in this paper uses simple hardware to ensure low power consumption thus maintaining longer battery life. This enables applications to use cheaper crystal that may be inaccurate and compensate for the inaccuracies within the hardware thus reducing board cost.

The Art of Pipelining

The ever-increasing demand for high speed ASICs is driving the requirement to increase circuit throughput in terms of calculations per clock cycle. The performance of an ASIC can be increased by pipelining but at an expense of increase in system latency and area.

Clocks and Resets

The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.

Low Power Design

In the good old days of IC design, before power became a significant design constraint, most chips were designed without concern for power consumption. This is not true anymore as requirements for lower power consumption continue to increase significantly as components become battery-powered, smaller and require more functionality.

The World of Metastability

In a synchronous system, the data always has a fixed relationship with respect to the clock. When that relationship obeys the setup and hold requirements for the device, the output goes to a valid state within its specified propagation delay time. In synchronous systems, the input signals always meet the flip-flop’s timing requirements; therefore, metastability does not occur. However, in an asynchronous system, the relationship between data and clock is not fixed; therefore, occasional violations of setup and hold times can occur. When this happens, the output may go to an intermediate level between its two valid states and remain there for an indefinite amount of time before resolving itself or it may simply be delayed before making a normal transition.

Design Guidelines for EMC Performance

Electronic circuits tend to pick up radiated signals from other transmitters whether these sources are transmitting intentionally or not. These Electromagnetic Interference or EMI problems can prevent adjacent piece of equipment working alongside one another. As a result it is necessary to design for Electromagnetic Compliance (EMC) to avoid harmful electromagnetic interference in the system.

Handling Multiple Clocks

Designs involving single clocks are easy and simple to implement. But in actual practice, there are few practical designs that function on just one clock. This chapter deals with multiple clock designs, problems faced therein and solutions in order to get a robust design that works on multiple clocks.