Mokhtar Aly

Thermal and Reliability Assessment for Wind Energy Systems With DSTATCOM Functionality in Resilient Microgrids

Different functionalities can be incorporated into wind energy conversion systems (WECSs) in resilient microgrids in order to reduce the total system cost and to assist their self-healing capability. Meanwhile, wind industry-based reliability surveys have addressed that power electronics components are the most vulnerable parts in WECS. Therefore, thermal stresses and lifetime consumption of WECS are critical factors for evaluating the added functionalities and for developing new control strategies as well. Almost all of the previous methodologies in the literature tackle the problem of lifetime assessment of WECS using only the behavior of wind generation profiles and reactive power injection, which is limited by grid codes. Subsequently, these approaches cannot efficiently achieve lifetime assessment in case of resilient microgrid operation and different load demands. This paper proposes a more convenient approach for thermal behavior, and lifetime assessment for WECSs that considers the influence of the added DSTATCOM functionality, and various modes of resilient microgrids operation. Moreover, the proposed approach utilizes a joint probability distribution function (JPDF) that combines both of the collected field data of wind generation and load demand levels as well. The feasibility of the proposed approach has been verified analytically and compared to the previously addressed approaches. It can be concluded that thermal behavior and reliability assessment of WECS are highly impacted by the added DSTATCOM functionality.

Thermal Stresses Relief Carrier-Based PWM Strategy for Single-Phase Multilevel Inverters

Enhancing power cycling capability of power semiconductor devices is highly demanded in order to increase the long-term reliability of multilevel inverters. Ageing of power switches and their cooling systems leads to their accelerated damage due to excess power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most effective solution for lifetime extension of power semiconductor devices. This paper presents a new TSR carrier-based pulse width modulation (TSRPWM) strategy for extending the lifetime of semiconductor switches in single-phase multilevel inverters. The proposed strategy benefits the inherent redundancy among switching states in multilevel inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains the inverter operation without increased stresses on healthy switches and without reduction of the output power ratings. In addition, the proposed algorithm preserves voltage balance of the dc-link capacitors. The proposed strategy is validated on a single-phase five-level T-type inverter system with considering different locations of thermal stresses detection. Experimental prototype of the selected case study is built to verify the results. Moreover, comparisons with the most featured strategies in literature are given in detail.

Reliability enhancement of multilevel inverters through SVPWM-based thermal management methodology

This paper introduces design and validation of space vector pulse width modulation (SVPWM) algorithm for reliability enhancement of multilevel inverters. Thermal overheating is the main cause of shortened-lifetime and open-circuit faults of power devices. It may result from ageing of semiconductor materials due to continuous operation and various operating conditions. Degradation and faults of cooling system are also of the major causes of overheating in power components. The proposed algorithm is applied when an overheating is detected in any of the semiconductor devices and helps to alleviate the overheating from the affected device and thereby preventing the overall system from malfunction. The proposed methodology relies on using the redundancy property between the switching states in multilevel inverters to continuously evaluate a cost function of the junction temperature of the overheated devices for all possible switching sequences, then it selects the optimal relieving switching sequence. Therefore, the lifetime of the overheated device can be considerably elongated. The proposed algorithm has been designed, simulated, and experimentally validated using a T-type three-level inverter system.

Design and validation of SVPWM algorithm for thermal protection of T-type three-level inverters

This paper investigates the design and validation of a new space vector pulse width modulation (SVPWM) algorithm for thermal protection of T-type three-level inverters. Thermal overheating is the main cause of shortened-lifetime and open-circuit faults of power devices. Power devices are subjected to thermal overheating due to degradation of power devices due to continuous overloading and power cycling, and degradation and faults in cooling systems. When a thermal overheating is detected in one of the switching devices, the proposed algorithm is applied to protect the thermally-overheated switch from being short/open-circuited and hence preventing the total system from malfunction. The lifetime and the reliability of the inverter have been enhanced considerably by a simple modification of the conventional SVPWM algorithm and without adding any additional hardware or complex calculations. In addition to that, the proposed algorithm does not deteriorate the inverters output current. The proposed thermal protection SVPWM algorithm has been designed, simulated, and experimentally validated at different operating conditions.

Lifetime-oriented SVPWM for thermally-overloaded power devices in three-level inverters

Boosting lifetime of power components in multilevel inverters is a major aim to enhance the total system reliability and performance. This paper presents a space vector pulse width modulation (SVPWM) strategy for lifetime prolongation of thermally-overloaded power devices in multilevel inverters. When a thermal overloading is detected in one of the power devices, the proposed algorithm is applied to relieve the overloaded device and therefore preventing dangerous circumstances such as open-or short-circuit faults. The proposed methodology relies on using the redundancy property between the switching states in multilevel inverters to continuously evaluate the junction temperature of the thermally-overloaded power devices for all the possible switching sequences, then it identifies the optimal relieving switching sequence. The proposed methodology is valid for both/either of the power switching devices and/or DC-link capacitors. The proposed strategy is simple, and does not require any additional hardware. Furthermore, it does not deteriorate the output power. Accordingly, lifetime and reliability of multilevel inverters have been enhanced considerably. The proposed methodology has been designed and validated by simulation and experimental prototyping of a three-level T-type inverter system to investigate its feasibility and effectiveness.

An enhanced PWM method for loss balancing of five level T-type inverter in PV systems

Multilevel inverters have attracted much industry and research concerns in photovoltaic (PV) applications. Although, it is demonstrated that power switching devices are subjected to unequal distribution of power losses and the reliability of multilevel inverters becomes low in accordance. Therefore, a new pulse width modulation (PWM) method is proposed in this paper for loss balancing in single phase five level inverters. The proposed method swaps the utilization of power components through the line period using the redundancy property between the switching states of T-type multilevel inverters. In addition, natural balance of voltages over DC link capacitors is achieved using the proposed method. The superiority of the proposed method is verified using simulation and experimental prototypes.

A New Single-Phase Five-Level Inverter Topology for Single and Multiple Switches Fault Tolerance

Reliability of power inverters is of dominant importance in various applications, including industrial, military, aerospace, and commercial applications. Therefore, developing fault tolerant (FT) power inverters is extremely needed from the viewpoints of system availability and avoiding harmful consequences. Tolerating various types of faults, preserving full output ratings after the fault, and being cost-effective represent the main challenges for most of existing FT solutions. In this paper, a new FT single-phase five-level inverter topology is proposed. The proposed topology can effectively tolerate both of single or multiple switches faults whether they are of open- or short-circuit fault types. Moreover, the proposed topology does not deteriorate system efficiency in postfault operation compared to the previously developed FT solutions. Evaluation of the effectiveness and robustness of the proposed topology is verified in both of simulation and experimental environments. Different case studies are investigated in order to cover various types and locations of switches’ faults. Moreover, comprehensive comparisons are provided to validate the superiority of the proposed topology over the previously addressed techniques.

An improved model predictive controller for highly reliable grid connected photovoltaic multilevel inverters

Multilevel Inverters play key role in grid integration of photovoltaic (PV) systems. Although power semiconductor devices in multilevel inverters represent the most expensive and vulnerable parts according to the recent reliability surveys. Thermal stresses in power semiconductor devices represent the main cause of their failures. Therefore, improved controllers with lower thermal stresses are highly demanded. Conventional finite control set model predictive control (MPC) utilizes a high sampling rate to select the optimum switching state from all possible states. Consequently, high power losses and high thermal stresses are produced in this type. This paper introduces an improved model predictive controller (MPC) for preserving high reliability for grid connected single phase full bridge five level T-type inverter. The proposed controller selects the optimum switching sequence to drive the inverter from a set of switching sequences with an optimized switching transitions. The proposed MPC features constant switching frequency with minimized switching transitions of power devices and voltage balance of DC-link capacitors. The results of the designed and implemented case study are presented to validate the superiority of the proposed controller.

A new real-time perfect condition monitoring for high-power converters

This paper presents a comprehensive online condition monitoring algorithm for power semiconductor devices. The proposed algorithm utilizes the voltage measurement between the collector and emitter of power semiconductor devices to fully monitor the performance and state of the device. The proposed algorithm provides four different detection and monitoring conditions of the device; these four elements are open-circuit fault detection, short circuit fault detection, overheating fault detection, remaining useful lifetime estimation. Compared to the previously addressed approaches in the literature, the proposed algorithm provides full state monitoring and detection of the device using only one sensed quantity. The collector-emitter voltage measurement of the device is chosen for implementing the proposed algorithm for its generality as it can be applied to various semiconductor devices technologies. Additionally, the proposed algorithm provides the advantages of simple implementation, comprehensive condition monitoring, and low cost. The implementation of the full proposed condition monitoring system is provided in the paper with case study application to boost DC-DC converter system. The results and comparisons of the proposed algorithm with previous strategies verify the feasibility of the proposed algorithm.

A unified SVM algorithm for lifetime prolongation of thermally-overheated power devices in multi-level inverters

This paper presents a unified space vector modulation (SVM) algorithm for lifetime prolongation of thermally-overheated power semiconductor devices in multilevel inverters. Thermal overheating is the main cause of shortened-lifetime and open-circuit faults of the devices. Power semiconductor devices are subjected to thermal overheating due to their ageing that results from continuous overloading and power cycling. Moreover, thermal overheating in high power devices may result from its degradation and faults in the cooling system. When a thermal overheating is detected in one of the power devices, the proposed algorithm is applied to relieve the overheated device and dangerous circumstances are avoided as a result. The proposed algorithm relies on using the redundancy property between switching states in multilevel inverters to continuously evaluate a cost function of the junction temperature of thermally-overheated device for all possible switching sequences set, then it identifies the optimal relieving switching sequence. The proposed unified SVM is general that can be applied to any multilevel inverter, and also is valid for switching devices, as well as DC-link capacitors. The proposed algorithm has been designed and validated by simulation and experimental prototypes of three-level T-type inverter.